/** @file\r
Header file for real time clock driver.\r
\r
-Copyright (c) 2006 - 2007, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
+Copyright (c) 2006 - 2007, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
#include <Library/UefiRuntimeLib.h>\r
#include <Library/UefiRuntimeServicesTableLib.h>\r
#include <Library/PcdLib.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
\r
\r
typedef struct {\r
// Register A\r
//\r
typedef struct {\r
- UINT8 RS : 4; // Rate Selection Bits\r
- UINT8 DV : 3; // Divisor\r
- UINT8 UIP : 1; // Update in progress\r
+ UINT8 Rs : 4; // Rate Selection Bits\r
+ UINT8 Dv : 3; // Divisor\r
+ UINT8 Uip : 1; // Update in progress\r
} RTC_REGISTER_A_BITS;\r
\r
typedef union {\r
// Register B\r
//\r
typedef struct {\r
- UINT8 DSE : 1; // 0 - Daylight saving disabled 1 - Daylight savings enabled\r
- UINT8 MIL : 1; // 0 - 12 hour mode 1 - 24 hour mode\r
- UINT8 DM : 1; // 0 - BCD Format 1 - Binary Format\r
- UINT8 SQWE : 1; // 0 - Disable SQWE output 1 - Enable SQWE output\r
- UINT8 UIE : 1; // 0 - Update INT disabled 1 - Update INT enabled\r
- UINT8 AIE : 1; // 0 - Alarm INT disabled 1 - Alarm INT Enabled\r
- UINT8 PIE : 1; // 0 - Periodic INT disabled 1 - Periodic INT Enabled\r
- UINT8 SET : 1; // 0 - Normal operation. 1 - Updates inhibited\r
+ UINT8 Dse : 1; // 0 - Daylight saving disabled 1 - Daylight savings enabled\r
+ UINT8 Mil : 1; // 0 - 12 hour mode 1 - 24 hour mode\r
+ UINT8 Dm : 1; // 0 - BCD Format 1 - Binary Format\r
+ UINT8 Sqwe : 1; // 0 - Disable SQWE output 1 - Enable SQWE output\r
+ UINT8 Uie : 1; // 0 - Update INT disabled 1 - Update INT enabled\r
+ UINT8 Aie : 1; // 0 - Alarm INT disabled 1 - Alarm INT Enabled\r
+ UINT8 Pie : 1; // 0 - Periodic INT disabled 1 - Periodic INT Enabled\r
+ UINT8 Set : 1; // 0 - Normal operation. 1 - Updates inhibited\r
} RTC_REGISTER_B_BITS;\r
\r
typedef union {\r
//\r
typedef struct {\r
UINT8 Reserved : 4; // Read as zero. Can not be written.\r
- UINT8 UF : 1; // Update End Interrupt Flag\r
- UINT8 AF : 1; // Alarm Interrupt Flag\r
- UINT8 PF : 1; // Periodic Interrupt Flag\r
- UINT8 IRQF : 1; // Iterrupt Request Flag = PF & PIE | AF & AIE | UF & UIE\r
+ UINT8 Uf : 1; // Update End Interrupt Flag\r
+ UINT8 Af : 1; // Alarm Interrupt Flag\r
+ UINT8 Pf : 1; // Periodic Interrupt Flag\r
+ UINT8 Irqf : 1; // Iterrupt Request Flag = PF & PIE | AF & AIE | UF & UIE\r
} RTC_REGISTER_C_BITS;\r
\r
typedef union {\r
//\r
typedef struct {\r
UINT8 Reserved : 7; // Read as zero. Can not be written.\r
- UINT8 VRT : 1; // Valid RAM and Time\r
+ UINT8 Vrt : 1; // Valid RAM and Time\r
} RTC_REGISTER_D_BITS;\r
\r
typedef union {\r