/** @file\r
- The Header file of the Pci Host Bridge Driver \r
+ The Header file of the Pci Host Bridge Driver\r
\r
- Copyright (c) 2008 - 2009, Intel Corporation<BR> All rights\r
- reserved. This program and the accompanying materials are\r
- licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
+ Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
- \r
+\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/ \r
+**/\r
\r
#ifndef _PCI_HOST_BRIDGE_H_\r
#define _PCI_HOST_BRIDGE_H_\r
\r
#include <Protocol/PciHostBridgeResourceAllocation.h>\r
#include <Protocol/PciRootBridgeIo.h>\r
-#include <Protocol/CpuIo2.h>\r
#include <Protocol/Metronome.h>\r
#include <Protocol/DevicePath.h>\r
\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DxeServicesTableLib.h>\r
#include <Library/DevicePathLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PciLib.h>\r
\r
//\r
// Hard code the host bridge number in the platform.\r
//\r
#define HOST_BRIDGE_NUMBER 1\r
\r
+#define MAX_PCI_DEVICE_NUMBER 31\r
+#define MAX_PCI_FUNCTION_NUMBER 7\r
+#define MAX_PCI_REG_ADDRESS 0xFF\r
+\r
+typedef enum {\r
+ IoOperation,\r
+ MemOperation,\r
+ PciOperation\r
+} OPERATION_TYPE;\r
+\r
#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't')\r
typedef struct {\r
UINTN Signature;\r
EFI_HANDLE HostBridgeHandle;\r
UINTN RootBridgeNumber;\r
LIST_ENTRY Head;\r
- BOOLEAN ResourceSubmited; \r
- BOOLEAN CanRestarted; \r
+ BOOLEAN ResourceSubmited;\r
+ BOOLEAN CanRestarted;\r
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;\r
} PCI_HOST_BRIDGE_INSTANCE;\r
\r
#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \\r
CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)\r
\r
-//\r
-// Driver Entry Point\r
-//\r
-EFI_STATUS\r
-EFIAPI\r
-EfiMain (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- );\r
- \r
//\r
// HostBridge Resource Allocation interface\r
//\r
+\r
+/**\r
+ These are the notifications from the PCI bus driver that it is about to enter\r
+ a certain phase of the PCI enumeration process.\r
+\r
+ This member function can be used to notify the host bridge driver to perform\r
+ specific actions, including any chipset-specific initialization, so that the\r
+ chipset is ready to enter the next phase. Eight notification points are\r
+ defined at this time. See belows:\r
+\r
+ EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures\r
+ and internal data structures. The PCI\r
+ enumerator should issue this\r
+ notification before starting a fresh\r
+ enumeration process. Enumeration\r
+ cannot be restarted after sending any\r
+ other notification such as\r
+ EfiPciHostBridgeBeginBusAllocation.\r
+\r
+ EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to\r
+ begin. No specific action is required\r
+ here. This notification can be used to\r
+ perform any chipset-specific\r
+ programming.\r
+\r
+ EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming\r
+ phase is complete. No specific action\r
+ is required here. This notification\r
+ can be used to perform any\r
+ chipset-specific programming.\r
+\r
+ EfiPciHostBridgeBeginResourceAllocation\r
+ The resource allocation phase is about\r
+ to begin. No specific action is\r
+ required here. This notification can\r
+ be used to perform any\r
+ chipset-specific programming.\r
+\r
+ EfiPciHostBridgeAllocateResources Allocates resources per previously\r
+ submitted requests for all the PCI\r
+ root bridges. These resource settings\r
+ are returned on the next call to\r
+ GetProposedResources(). Before calling\r
+ NotifyPhase() with a Phase of\r
+ EfiPciHostBridgeAllocateResource, the\r
+ PCI bus enumerator is responsible for\r
+ gathering I/O and memory requests for\r
+ all the PCI root bridges and\r
+ submitting these requests using\r
+ SubmitResources(). This function pads\r
+ the resource amount to suit the root\r
+ bridge hardware, takes care of\r
+ dependencies between the PCI root\r
+ bridges, and calls the Global\r
+ Coherency Domain (GCD) with the\r
+ allocation request. In the case of\r
+ padding, the allocated range could be\r
+ bigger than what was requested.\r
+\r
+ EfiPciHostBridgeSetResources Programs the host bridge hardware to\r
+ decode previously allocated resources\r
+ (proposed resources) for all the PCI\r
+ root bridges. After the hardware is\r
+ programmed, reassigning resources will\r
+ not be supported. The bus settings are\r
+ not affected.\r
+\r
+ EfiPciHostBridgeFreeResources Deallocates resources that were\r
+ previously allocated for all the PCI\r
+ root bridges and resets the I/O and\r
+ memory apertures to their initial\r
+ state. The bus settings are not\r
+ affected. If the request to allocate\r
+ resources fails, the PCI enumerator\r
+ can use this notification to\r
+ deallocate previous resources, adjust\r
+ the requests, and retry allocation.\r
+\r
+ EfiPciHostBridgeEndResourceAllocation The resource allocation phase is\r
+ completed. No specific action is\r
+ required here. This notification can\r
+ be used to perform any chipsetspecific\r
+ programming.\r
+\r
+ @param[in] This The instance pointer of\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+\r
+ @param[in] Phase The phase during enumeration\r
+\r
+ @retval EFI_NOT_READY This phase cannot be entered at this time. For\r
+ example, this error is valid for a Phase of\r
+ EfiPciHostBridgeAllocateResources if\r
+ SubmitResources() has not been called for one\r
+ or more PCI root bridges before this call\r
+\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+ This error is valid for a Phase of\r
+ EfiPciHostBridgeSetResources.\r
+\r
+ @retval EFI_INVALID_PARAMETER Invalid phase parameter\r
+\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
+ lack of resources. This error is valid for a\r
+ Phase of EfiPciHostBridgeAllocateResources if\r
+ the previously submitted resource requests\r
+ cannot be fulfilled or were only partially\r
+ fulfilled.\r
+\r
+ @retval EFI_SUCCESS The notification was accepted without any\r
+ errors.\r
+**/\r
EFI_STATUS\r
EFIAPI\r
NotifyPhase(\r
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
);\r
\r
+/**\r
+ Return the device handle of the next PCI root bridge that is associated with\r
+ this Host Bridge.\r
+\r
+ This function is called multiple times to retrieve the device handles of all\r
+ the PCI root bridges that are associated with this PCI host bridge. Each PCI\r
+ host bridge is associated with one or more PCI root bridges. On each call,\r
+ the handle that was returned by the previous call is passed into the\r
+ interface, and on output the interface returns the device handle of the next\r
+ PCI root bridge. The caller can use the handle to obtain the instance of the\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL for that root bridge. When there are no more\r
+ PCI root bridges to report, the interface returns EFI_NOT_FOUND. A PCI\r
+ enumerator must enumerate the PCI root bridges in the order that they are\r
+ returned by this function.\r
+\r
+ For D945 implementation, there is only one root bridge in PCI host bridge.\r
+\r
+ @param[in] This The instance pointer of\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+\r
+ @param[in, out] RootBridgeHandle Returns the device handle of the next PCI\r
+ root bridge.\r
+\r
+ @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then\r
+ return the first Rootbridge handle of the\r
+ specific Host bridge and return EFI_SUCCESS.\r
+\r
+ @retval EFI_NOT_FOUND Can not find the any more root bridge in\r
+ specific host bridge.\r
+\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was\r
+ returned on a previous call to\r
+ GetNextRootBridge().\r
+**/\r
EFI_STATUS\r
EFIAPI\r
GetNextRootBridge(\r
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
IN OUT EFI_HANDLE *RootBridgeHandle\r
);\r
- \r
+\r
+/**\r
+ Returns the allocation attributes of a PCI root bridge.\r
+\r
+ The function returns the allocation attributes of a specific PCI root bridge.\r
+ The attributes can vary from one PCI root bridge to another. These attributes\r
+ are different from the decode-related attributes that are returned by the\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The\r
+ RootBridgeHandle parameter is used to specify the instance of the PCI root\r
+ bridge. The device handles of all the root bridges that are associated with\r
+ this host bridge must be obtained by calling GetNextRootBridge(). The\r
+ attributes are static in the sense that they do not change during or after\r
+ the enumeration process. The hardware may provide mechanisms to change the\r
+ attributes on the fly, but such changes must be completed before\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is installed. The permitted\r
+ values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in\r
+ "Related Definitions" below. The caller uses these attributes to combine\r
+ multiple resource requests.\r
+\r
+ For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI\r
+ bus enumerator needs to include requests for the prefetchable memory in the\r
+ nonprefetchable memory pool and not request any prefetchable memory.\r
+\r
+ Attribute Description\r
+ ------------------------------------ ---------------------------------------\r
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root\r
+ bridge does not support separate\r
+ windows for nonprefetchable and\r
+ prefetchable memory. A PCI bus driver\r
+ needs to include requests for\r
+ prefetchable memory in the\r
+ nonprefetchable memory pool.\r
+\r
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root\r
+ bridge supports 64-bit memory windows.\r
+ If this bit is not set, the PCI bus\r
+ driver needs to include requests for a\r
+ 64-bit memory address in the\r
+ corresponding 32-bit memory pool.\r
+\r
+ @param[in] This The instance pointer of\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+\r
+ @param[in] RootBridgeHandle The device handle of the PCI root bridge in\r
+ which the caller is interested. Type\r
+ EFI_HANDLE is defined in\r
+ InstallProtocolInterface() in the UEFI 2.0\r
+ Specification.\r
+\r
+ @param[out] Attributes The pointer to attribte of root bridge, it is\r
+ output parameter\r
+\r
+ @retval EFI_INVALID_PARAMETER Attribute pointer is NULL\r
+\r
+ @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.\r
+\r
+ @retval EFI_SUCCESS Success to get attribute of interested root\r
+ bridge.\r
+**/\r
EFI_STATUS\r
EFIAPI\r
GetAttributes(\r
IN EFI_HANDLE RootBridgeHandle,\r
OUT UINT64 *Attributes\r
);\r
- \r
+\r
+/**\r
+ Sets up the specified PCI root bridge for the bus enumeration process.\r
+\r
+ This member function sets up the root bridge for bus enumeration and returns\r
+ the PCI bus range over which the search should be performed in ACPI 2.0\r
+ resource descriptor format.\r
+\r
+ @param[in] This The\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ instance.\r
+\r
+ @param[in] RootBridgeHandle The PCI Root Bridge to be set up.\r
+\r
+ @param[out] Configuration Pointer to the pointer to the PCI bus resource\r
+ descriptor.\r
+\r
+ @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle\r
+\r
+ @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.\r
+\r
+ @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.\r
+**/\r
EFI_STATUS\r
EFIAPI\r
StartBusEnumeration(\r
IN EFI_HANDLE RootBridgeHandle,\r
OUT VOID **Configuration\r
);\r
- \r
+\r
+/**\r
+ Programs the PCI root bridge hardware so that it decodes the specified PCI\r
+ bus range.\r
+\r
+ This member function programs the specified PCI root bridge to decode the bus\r
+ range that is specified by the input parameter Configuration.\r
+ The bus range information is specified in terms of the ACPI 2.0 resource\r
+ descriptor format.\r
+\r
+ @param[in] This The\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ instance\r
+\r
+ @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be\r
+ programmed\r
+\r
+ @param[in] Configuration The pointer to the PCI bus resource descriptor\r
+\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge\r
+ handle.\r
+\r
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
+\r
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI\r
+ 2.0 resource descriptor.\r
+\r
+ @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI\r
+ 2.0 bus resource descriptor.\r
+\r
+ @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource\r
+ descriptors other than bus descriptors.\r
+\r
+ @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid\r
+ ACPI resource descriptors.\r
+\r
+ @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this\r
+ root bridge.\r
+\r
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this\r
+ root bridge.\r
+\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+\r
+ @retval EFI_SUCCESS The bus range for the PCI root bridge was\r
+ programmed.\r
+**/\r
EFI_STATUS\r
EFIAPI\r
SetBusNumbers(\r
IN EFI_HANDLE RootBridgeHandle,\r
IN VOID *Configuration\r
);\r
- \r
+\r
+/**\r
+ Submits the I/O and memory resource requirements for the specified PCI root\r
+ bridge.\r
+\r
+ This function is used to submit all the I/O and memory resources that are\r
+ required by the specified PCI root bridge. The input parameter Configuration\r
+ is used to specify the following:\r
+ - The various types of resources that are required\r
+ - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
+\r
+ @param[in] This Pointer to the\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ instance.\r
+\r
+ @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory\r
+ resource requirements are being submitted.\r
+\r
+ @param[in] Configuration The pointer to the PCI I/O and PCI memory\r
+ resource descriptor.\r
+\r
+ @retval EFI_SUCCESS The I/O and memory resource requests for a PCI\r
+ root bridge were accepted.\r
+\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge\r
+ handle.\r
+\r
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
+\r
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI\r
+ 2.0 resource descriptor.\r
+\r
+ @retval EFI_INVALID_PARAMETER Configuration includes requests for one or\r
+ more resource types that are not supported by\r
+ this PCI root bridge. This error will happen\r
+ if the caller did not combine resources\r
+ according to Attributes that were returned by\r
+ GetAllocAttributes().\r
+\r
+ @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.\r
+\r
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI\r
+ root bridge.\r
+\r
+ @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for\r
+ this PCI root bridge.\r
+**/\r
EFI_STATUS\r
EFIAPI\r
SubmitResources(\r
IN EFI_HANDLE RootBridgeHandle,\r
IN VOID *Configuration\r
);\r
- \r
+\r
+/**\r
+ Returns the proposed resource settings for the specified PCI root bridge.\r
+\r
+ This member function returns the proposed resource settings for the\r
+ specified PCI root bridge. The proposed resource settings are prepared when\r
+ NotifyPhase() is called with a Phase of EfiPciHostBridgeAllocateResources.\r
+ The output parameter Configuration specifies the following:\r
+ - The various types of resources, excluding bus resources, that are\r
+ allocated\r
+ - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
+\r
+ @param[in] This Pointer to the\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ instance.\r
+\r
+ @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is\r
+ defined in InstallProtocolInterface() in the\r
+ UEFI 2.0 Specification.\r
+\r
+ @param[out] Configuration The pointer to the pointer to the PCI I/O and\r
+ memory resource descriptor.\r
+\r
+ @retval EFI_SUCCESS The requested parameters were returned.\r
+\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge\r
+ handle.\r
+\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
+ lack of resources.\r
+**/\r
EFI_STATUS\r
EFIAPI\r
GetProposedResources(\r
OUT VOID **Configuration\r
);\r
\r
+/**\r
+ Provides the hooks from the PCI bus driver to every PCI controller\r
+ (device/function) at various stages of the PCI enumeration process that allow\r
+ the host bridge driver to preinitialize individual PCI controllers before\r
+ enumeration.\r
+\r
+ This function is called during the PCI enumeration process. No specific\r
+ action is expected from this member function. It allows the host bridge\r
+ driver to preinitialize individual PCI controllers before enumeration.\r
+\r
+ @param This Pointer to the\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ instance.\r
+\r
+ @param RootBridgeHandle The associated PCI root bridge handle. Type\r
+ EFI_HANDLE is defined in InstallProtocolInterface()\r
+ in the UEFI 2.0 Specification.\r
+\r
+ @param PciAddress The address of the PCI device on the PCI bus. This\r
+ address can be passed to the\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to\r
+ access the PCI configuration space of the device.\r
+ See Table 12-1 in the UEFI 2.0 Specification for the\r
+ definition of\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.\r
+\r
+ @param Phase The phase of the PCI device enumeration.\r
+\r
+ @retval EFI_SUCCESS The requested parameters were returned.\r
+\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge\r
+ handle.\r
+\r
+ @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined\r
+ in\r
+ EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
+\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+ The PCI enumerator should not enumerate this\r
+ device, including its child devices if it is\r
+ a PCI-to-PCI bridge.\r
+**/\r
EFI_STATUS\r
EFIAPI\r
PreprocessController (\r
\r
\r
//\r
-// Define resource status constant \r
+// Define resource status constant\r
//\r
#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r
#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r
\r
typedef struct {\r
UINT64 BusBase;\r
- UINT64 BusLimit; \r
- \r
- UINT64 MemBase; \r
- UINT64 MemLimit; \r
- \r
- UINT64 IoBase; \r
- UINT64 IoLimit; \r
-} PCI_ROOT_BRIDGE_RESOURCE_APPETURE;\r
+ UINT64 BusLimit;\r
+\r
+ UINT64 MemBase;\r
+ UINT64 MemLimit;\r
+\r
+ UINT64 IoBase;\r
+ UINT64 IoLimit;\r
+} PCI_ROOT_BRIDGE_RESOURCE_APERTURE;\r
\r
typedef enum {\r
TypeIo = 0,\r
UINT64 RootBridgeAttrib;\r
UINT64 Attributes;\r
UINT64 Supports;\r
- \r
+\r
//\r
// Specific for this memory controller: Bus, I/O, Mem\r
//\r
PCI_RES_NODE ResAllocNode[6];\r
- \r
+\r
//\r
// Addressing for Memory and I/O and Bus arrange\r
//\r
UINT64 BusBase;\r
- UINT64 MemBase; \r
- UINT64 IoBase; \r
- UINT64 BusLimit; \r
- UINT64 MemLimit; \r
- UINT64 IoLimit; \r
-\r
- EFI_LOCK PciLock;\r
- UINTN PciAddress;\r
- UINTN PciData;\r
- \r
+ UINT64 MemBase;\r
+ UINT64 IoBase;\r
+ UINT64 BusLimit;\r
+ UINT64 MemLimit;\r
+ UINT64 IoLimit;\r
+\r
EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;\r
\r
#define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \\r
CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)\r
\r
+/**\r
+\r
+ Construct the Pci Root Bridge Io protocol\r
+\r
+ @param Protocol Point to protocol instance\r
+ @param HostBridgeHandle Handle of host bridge\r
+ @param Attri Attribute of host bridge\r
+ @param ResAperture ResourceAperture for host bridge\r
\r
+ @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.\r
+**/\r
EFI_STATUS\r
RootBridgeConstructor (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,\r
IN EFI_HANDLE HostBridgeHandle,\r
IN UINT64 Attri,\r
- IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture\r
+ IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture\r
);\r
\r
#endif\r
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