/** @file\r
PCI Root Bridge Io Protocol implementation\r
\r
-Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials are\r
licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
**/ \r
\r
#include "PciHostBridge.h"\r
+#include "IoFifo.h"\r
\r
typedef struct {\r
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp[TypeMax];\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
IN UINTN Count,\r
- IN OUT VOID *Buffer\r
+ OUT VOID *Buffer\r
);\r
\r
/**\r
responsible for aligning the Address if required.\r
@param[in] Count The number of memory operations to perform. Bytes moved is\r
Width size * Count, starting at Address.\r
- @param[out] Buffer For read operations, the destination buffer to store the results. For\r
+ @param[in] Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
IN UINTN Count,\r
- IN OUT VOID *Buffer\r
+ IN VOID *Buffer\r
);\r
\r
/**\r
\r
@param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
@param[in] Width Signifies the width of the memory operations.\r
- @param[in] Address The base address of the I/O operation. The caller is responsible for\r
+ @param[in] UserAddress The base address of the I/O operation. The caller is responsible for\r
aligning the Address if required.\r
@param[in] Count The number of I/O operations to perform. Bytes moved is Width\r
size * Count, starting at Address.\r
- @param[out] Buffer For read operations, the destination buffer to store the results. For\r
+ @param[out] UserBuffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 UserAddress,\r
IN UINTN Count,\r
- IN OUT VOID *UserBuffer\r
+ OUT VOID *UserBuffer\r
);\r
\r
/**\r
\r
@param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
@param[in] Width Signifies the width of the memory operations.\r
- @param[in] Address The base address of the I/O operation. The caller is responsible for\r
+ @param[in] UserAddress The base address of the I/O operation. The caller is responsible for\r
aligning the Address if required.\r
@param[in] Count The number of I/O operations to perform. Bytes moved is Width\r
size * Count, starting at Address.\r
- @param[out] Buffer For read operations, the destination buffer to store the results. For\r
+ @param[in] UserBuffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 UserAddress,\r
IN UINTN Count,\r
- IN OUT VOID *UserBuffer\r
+ IN VOID *UserBuffer\r
);\r
\r
/**\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
IN UINTN Count,\r
- IN OUT VOID *Buffer\r
+ OUT VOID *Buffer\r
);\r
\r
/**\r
@param[in] Address The address within the PCI configuration space for the PCI controller.\r
@param[in] Count The number of PCI configuration operations to perform. Bytes\r
moved is Width size * Count, starting at Address.\r
- @param[out] Buffer For read operations, the destination buffer to store the results. For\r
+ @param[in] Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
IN UINTN Count,\r
- IN OUT VOID *Buffer\r
+ IN VOID *Buffer\r
);\r
\r
/**\r
@param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
@param[in] Operation Indicates if the bus master is going to read or write to system memory.\r
@param[in] HostAddress The system memory address to map to the PCI controller.\r
- @param[in][out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.\r
+ @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.\r
@param[out] DeviceAddress The resulting map address for the bus master PCI controller to use\r
to access the system memory's HostAddress.\r
@param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.\r
MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
MEMORY_DISABLE are not set, then ResourceBase and\r
ResourceLength are ignored, and may be NULL.\r
- @param[in][out] ResourceBase A pointer to the base address of the resource range to be modified\r
+ @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified\r
by the attributes specified by Attributes.\r
- @param[in][out] ResourceLength A pointer to the length of the resource range to be modified by the\r
+ @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the\r
attributes specified by Attributes.\r
\r
@retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.\r
\r
PrivateData->RootBridgeAttrib = Attri;\r
\r
- PrivateData->Attributes = 0;\r
- PrivateData->Supports = 0;\r
+ PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \\r
+ EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \\r
+ EFI_PCI_ATTRIBUTE_VGA_MEMORY | \\r
+ EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ PrivateData->Attributes = PrivateData->Supports;\r
\r
Protocol->ParentHandle = HostBridgeHandle;\r
\r
//\r
// Check to see if Width is in the valid range\r
//\r
- if (Width < EfiPciWidthUint8 || Width >= EfiPciWidthMaximum) {\r
+ if ((UINT32)Width >= EfiPciWidthMaximum) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
@param[in] UserAddress The address within the PCI configuration space for the PCI controller.\r
@param[in] Count The number of PCI configuration operations to perform. Bytes\r
moved is Width size * Count, starting at Address.\r
- @param[out] UserBuffer For read operations, the destination buffer to store the results. For\r
+ @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
case EfiPciWidthUint64:\r
MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));\r
break;\r
+ default:\r
+ //\r
+ // The RootBridgeIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
}\r
} else {\r
switch (OperationWidth) {\r
case EfiPciWidthUint64:\r
*((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);\r
break;\r
+ default:\r
+ //\r
+ // The RootBridgeIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
}\r
}\r
}\r
@param[in] UserAddress The address within the PCI configuration space for the PCI controller.\r
@param[in] Count The number of PCI configuration operations to perform. Bytes\r
moved is Width size * Count, starting at Address.\r
- @param[out] UserBuffer For read operations, the destination buffer to store the results. For\r
+ @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
InStride = mInStride[Width];\r
OutStride = mOutStride[Width];\r
OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+\r
+#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
+ if (InStride == 0) {\r
+ if (Write) {\r
+ switch (OperationWidth) {\r
+ case EfiPciWidthUint8:\r
+ IoWriteFifo8 ((UINTN) Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiPciWidthUint16:\r
+ IoWriteFifo16 ((UINTN) Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiPciWidthUint32:\r
+ IoWriteFifo32 ((UINTN) Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ default:\r
+ //\r
+ // The RootBridgeIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
+ }\r
+ } else {\r
+ switch (OperationWidth) {\r
+ case EfiPciWidthUint8:\r
+ IoReadFifo8 ((UINTN) Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiPciWidthUint16:\r
+ IoReadFifo16 ((UINTN) Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiPciWidthUint32:\r
+ IoReadFifo32 ((UINTN) Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ default:\r
+ //\r
+ // The RootBridgeIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
+ }\r
+ }\r
+ }\r
+#endif\r
+\r
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (Write) {\r
switch (OperationWidth) {\r
case EfiPciWidthUint32:\r
IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
break;\r
+ default:\r
+ //\r
+ // The RootBridgeIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
}\r
} else {\r
switch (OperationWidth) {\r
case EfiPciWidthUint32:\r
*((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address);\r
break;\r
+ default:\r
+ //\r
+ // The RootBridgeIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
}\r
}\r
}\r
@param[in] UserAddress The address within the PCI configuration space for the PCI controller.\r
@param[in] Count The number of PCI configuration operations to perform. Bytes\r
moved is Width size * Count, starting at Address.\r
- @param[out] UserBuffer For read operations, the destination buffer to store the results. For\r
+ @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
case EfiPciWidthUint32:\r
PciWrite32 (PcieRegAddr, *((UINT32 *)Uint8Buffer));\r
break;\r
+ default:\r
+ //\r
+ // The RootBridgeIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
}\r
} else {\r
switch (OperationWidth) {\r
case EfiPciWidthUint32:\r
*((UINT32 *)Uint8Buffer) = PciRead32 (PcieRegAddr);\r
break;\r
+ default:\r
+ //\r
+ // The RootBridgeIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
}\r
}\r
}\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- if (Width < 0 || Width > EfiPciWidthUint64) {\r
+ if ((UINT32)Width > EfiPciWidthUint64) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
}\r
NumberOfTicks += 1;\r
\r
- while (NumberOfTicks) {\r
+ while (NumberOfTicks != 0) {\r
\r
mMetronome->WaitForTick (mMetronome, 1);\r
\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- if (Width < 0 || Width > EfiPciWidthUint64) {\r
+ if ((UINT32)Width > EfiPciWidthUint64) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
}\r
NumberOfTicks += 1;\r
\r
- while (NumberOfTicks) {\r
+ while (NumberOfTicks != 0) {\r
\r
mMetronome->WaitForTick (mMetronome, 1);\r
\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
IN UINTN Count,\r
- IN OUT VOID *Buffer\r
+ OUT VOID *Buffer\r
)\r
{\r
return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer);\r
responsible for aligning the Address if required.\r
@param[in] Count The number of memory operations to perform. Bytes moved is\r
Width size * Count, starting at Address.\r
- @param[out] Buffer For read operations, the destination buffer to store the results. For\r
+ @param[in] Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
IN UINTN Count,\r
- IN OUT VOID *Buffer\r
+ IN VOID *Buffer\r
)\r
{\r
return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer); \r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
IN UINTN Count,\r
- IN OUT VOID *Buffer\r
+ OUT VOID *Buffer\r
)\r
{\r
return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer); \r
aligning the Address if required.\r
@param[in] Count The number of I/O operations to perform. Bytes moved is Width\r
size * Count, starting at Address.\r
- @param[out] Buffer For read operations, the destination buffer to store the results. For\r
+ @param[in] Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
IN UINTN Count,\r
- IN OUT VOID *Buffer\r
+ IN VOID *Buffer\r
)\r
{\r
return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer); \r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoCopyMem (\r
- IN struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 DestAddress,\r
IN UINT64 SrcAddress,\r
UINTN Index;\r
UINT64 Result;\r
\r
- if (Width < 0 || Width > EfiPciWidthUint64) {\r
+ if ((UINT32)Width > EfiPciWidthUint64) {\r
return EFI_INVALID_PARAMETER;\r
} \r
\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
IN UINTN Count,\r
- IN OUT VOID *Buffer\r
+ OUT VOID *Buffer\r
)\r
{\r
return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);\r
@param[in] Address The address within the PCI configuration space for the PCI controller.\r
@param[in] Count The number of PCI configuration operations to perform. Bytes\r
moved is Width size * Count, starting at Address.\r
- @param[out] Buffer For read operations, the destination buffer to store the results. For\r
+ @param[in] Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
IN UINT64 Address,\r
IN UINTN Count,\r
- IN OUT VOID *Buffer\r
+ IN VOID *Buffer\r
)\r
{\r
return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);\r
@param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
@param[in] Operation Indicates if the bus master is going to read or write to system memory.\r
@param[in] HostAddress The system memory address to map to the PCI controller.\r
- @param[in][out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.\r
+ @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.\r
@param[out] DeviceAddress The resulting map address for the bus master PCI controller to use\r
to access the system memory's HostAddress.\r
@param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.\r
//\r
// Make sure that Operation is valid\r
//\r
- if (Operation < 0 || Operation >= EfiPciOperationMaximum) {\r
+ if ((UINT32)Operation >= EfiPciOperationMaximum) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
//\r
// Validate Attributes\r
//\r
- if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {\r
+ if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {\r
return EFI_UNSUPPORTED;\r
}\r
\r
//\r
// Set the return value for Supported and Attributes\r
//\r
- if (Supported) {\r
+ if (Supported != NULL) {\r
*Supported = PrivateData->Supports; \r
}\r
\r
- if (Attributes) {\r
+ if (Attributes != NULL) {\r
*Attributes = PrivateData->Attributes;\r
}\r
\r
MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
MEMORY_DISABLE are not set, then ResourceBase and\r
ResourceLength are ignored, and may be NULL.\r
- @param[in][out] ResourceBase A pointer to the base address of the resource range to be modified\r
+ @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified\r
by the attributes specified by Attributes.\r
- @param[in][out] ResourceLength A pointer to the length of the resource range to be modified by the\r
+ @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the\r
attributes specified by Attributes.\r
\r
@retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.\r
\r
PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
\r
- if (Attributes) {\r
+ if (Attributes != 0) {\r
if ((Attributes & (~(PrivateData->Supports))) != 0) {\r
return EFI_UNSUPPORTED;\r
}\r
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