/// Cache parameters allowed by the architecture with\r
/// ARMv8.3-CCIDX (Cache extended number of sets)\r
/// Derived from CCSIDR_EL1 when ID_AA64MMFR2_EL1.CCIDX==0001\r
-#define PPTT_ARM_CCIDX_CACHE_NUMBER_OF_SETS_MAX (1 << 24)\r
-#define PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX (1 << 21)\r
+#define PPTT_ARM_CCIDX_CACHE_NUMBER_OF_SETS_MAX (1 << 24)\r
+#define PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX (1 << 21)\r
\r
/// Cache parameters allowed by the architecture without\r
/// ARMv8.3-CCIDX (Cache extended number of sets)\r
/// Derived from CCSIDR_EL1 when ID_AA64MMFR2_EL1.CCIDX==0000\r
-#define PPTT_ARM_CACHE_NUMBER_OF_SETS_MAX (1 << 15)\r
-#define PPTT_ARM_CACHE_ASSOCIATIVITY_MAX (1 << 10)\r
+#define PPTT_ARM_CACHE_NUMBER_OF_SETS_MAX (1 << 15)\r
+#define PPTT_ARM_CACHE_ASSOCIATIVITY_MAX (1 << 10)\r
\r
/// Common cache parameters\r
/// Derived from CCSIDR_EL1\r
/// The LineSize is represented by bits 2:0\r
/// (Log2(Number of bytes in cache line)) - 4 is used to represent\r
/// the LineSize bits.\r
-#define PPTT_ARM_CACHE_LINE_SIZE_MAX (1 << 11)\r
-#define PPTT_ARM_CACHE_LINE_SIZE_MIN (1 << 4)\r
+#define PPTT_ARM_CACHE_LINE_SIZE_MAX (1 << 11)\r
+#define PPTT_ARM_CACHE_LINE_SIZE_MIN (1 << 4)\r
\r
#endif // if defined (MDE_CPU_ARM) || defined (MDE_CPU_AARCH64)\r
\r