/** @file\r
Main file for Pci shell Debug1 function.\r
\r
- Copyright (c) 2005 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2005 - 2018, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>\r
- (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR> \r
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
@param[in] ConfigSpace Data in PCI configuration space.\r
@param[in] Address Address used to access configuration space of this PCI device.\r
@param[in] IoDev Handle used to access configuration space of PCI device.\r
- @param[in] EnhancedDump The print format for the dump data.\r
-\r
- @retval EFI_SUCCESS The command completed successfully.\r
**/\r
-EFI_STATUS\r
-PciExplainData (\r
+VOID\r
+PciExplainPci (\r
IN PCI_CONFIG_SPACE *ConfigSpace,\r
IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
- IN CONST UINT16 EnhancedDump\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
);\r
\r
/**\r
);\r
\r
/**\r
- Print each capability structure.\r
+ Locate capability register block per capability ID.\r
\r
- @param[in] IoDev The pointer to the deivce.\r
- @param[in] Address The address to start at.\r
- @param[in] CapPtr The offset from the address.\r
- @param[in] EnhancedDump The print format for the dump data.\r
+ @param[in] ConfigSpace Data in PCI configuration space.\r
+ @param[in] CapabilityId The capability ID.\r
\r
- @retval EFI_SUCCESS The operation was successful.\r
+ @return The offset of the register block per capability ID.\r
**/\r
-EFI_STATUS\r
-PciExplainCapabilityStruct (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
- IN UINT64 Address,\r
- IN UINT8 CapPtr,\r
- IN CONST UINT16 EnhancedDump\r
+UINT8\r
+LocatePciCapability (\r
+ IN PCI_CONFIG_SPACE *ConfigSpace,\r
+ IN UINT8 CapabilityId\r
);\r
\r
/**\r
Display Pcie device structure.\r
\r
- @param[in] IoDev The pointer to the root pci protocol.\r
- @param[in] Address The Address to start at.\r
- @param[in] CapabilityPtr The offset from the address to start.\r
- @param[in] EnhancedDump The print format for the dump data.\r
- \r
- @retval EFI_SUCCESS The command completed successfully.\r
- @retval @retval EFI_SUCCESS Pci express extend space IO is not suppoted. \r
+ @param[in] PciExpressCap PCI Express capability buffer.\r
+ @param[in] ExtendedConfigSpace PCI Express extended configuration space.\r
+ @param[in] ExtendedCapability PCI Express extended capability ID to explain.\r
**/\r
-EFI_STATUS\r
+VOID\r
PciExplainPciExpress (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
- IN UINT64 Address,\r
- IN UINT8 CapabilityPtr,\r
- IN CONST UINT16 EnhancedDump\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap,\r
+ IN UINT8 *ExtendedConfigSpace,\r
+ IN CONST UINT16 ExtendedCapability\r
);\r
\r
/**\r
SHELL_STATUS ShellStatus;\r
CONST CHAR16 *Temp;\r
UINT64 RetVal;\r
- UINT16 EnhancedDump;\r
+ UINT16 ExtendedCapability;\r
+ UINT8 PcieCapabilityPtr;\r
+ UINT8 *ExtendedConfigSpace;\r
+ UINTN ExtendedConfigSize;\r
\r
ShellStatus = SHELL_SUCCESS;\r
Status = EFI_SUCCESS;\r
Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
if (EFI_ERROR(Status)) {\r
if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, L"pci", ProblemParam); \r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, L"pci", ProblemParam);\r
FreePool(ProblemParam);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
} else {\r
} else {\r
\r
if (ShellCommandLineGetCount(Package) == 2) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle, L"pci"); \r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle, L"pci");\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
if (ShellCommandLineGetCount(Package) > 4) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"pci"); \r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"pci");\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
if (ShellCommandLineGetFlag(Package, L"-ec") && ShellCommandLineGetValue(Package, L"-ec") == NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-ec"); \r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-ec");\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-s"); \r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-s");\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
HandleBufSize = sizeof (EFI_HANDLE);\r
HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r
if (HandleBuf == NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci"); \r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci");\r
ShellStatus = SHELL_OUT_OF_RESOURCES;\r
goto Done;\r
}\r
if (Status == EFI_BUFFER_TOO_SMALL) {\r
HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r
if (HandleBuf == NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci"); \r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci");\r
ShellStatus = SHELL_OUT_OF_RESOURCES;\r
goto Done;\r
}\r
}\r
\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle, L"pci"); \r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle, L"pci");\r
ShellStatus = SHELL_NOT_FOUND;\r
goto Done;\r
}\r
&Descriptors\r
);\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, L"pci"); \r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, L"pci");\r
ShellStatus = SHELL_NOT_FOUND;\r
goto Done;\r
}\r
Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, L"pci"); \r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, L"pci");\r
ShellStatus = SHELL_NOT_FOUND;\r
goto Done;\r
}\r
Bus = 0;\r
Device = 0;\r
Func = 0;\r
+ ExtendedCapability = 0xFFFF;\r
if (ShellCommandLineGetFlag(Package, L"-i")) {\r
ExplainData = TRUE;\r
}\r
if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
Segment = (UINT16) RetVal;\r
} else {\r
- ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
Bus = (UINT16) RetVal;\r
} else {\r
- ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
if (Bus > PCI_MAX_BUS) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
Device = (UINT16) RetVal;\r
} else {\r
- ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
if (Device > PCI_MAX_DEVICE){\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
Func = (UINT16) RetVal;\r
} else {\r
- ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
if (Func > PCI_MAX_FUNC){\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);\r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
+ }\r
+\r
+ Temp = ShellCommandLineGetValue (Package, L"-ec");\r
+ if (Temp != NULL) {\r
+ //\r
+ // Input converted to hexadecimal number.\r
+ //\r
+ if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
+ ExtendedCapability = (UINT16) RetVal;\r
+ } else {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
if (EFI_ERROR (Status)) {\r
ShellPrintHiiEx(\r
- -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle, L"pci", \r
+ -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle, L"pci",\r
Segment,\r
Bus\r
);\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, L"pci"); \r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, L"pci");\r
ShellStatus = SHELL_ACCESS_DENIED;\r
goto Done;\r
}\r
ConfigSpace.Data\r
);\r
\r
+ ExtendedConfigSpace = NULL;\r
+ ExtendedConfigSize = 0;\r
+ PcieCapabilityPtr = LocatePciCapability (&ConfigSpace, EFI_PCI_CAPABILITY_ID_PCIEXP);\r
+ if (PcieCapabilityPtr != 0) {\r
+ ExtendedConfigSize = 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET;\r
+ ExtendedConfigSpace = AllocatePool (ExtendedConfigSize);\r
+ if (ExtendedConfigSpace != NULL) {\r
+ Status = IoDev->Pci.Read (\r
+ IoDev,\r
+ EfiPciWidthUint32,\r
+ EFI_PCI_ADDRESS (Bus, Device, Func, EFI_PCIE_CAPABILITY_BASE_OFFSET),\r
+ ExtendedConfigSize / sizeof (UINT32),\r
+ ExtendedConfigSpace\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ SHELL_FREE_NON_NULL (ExtendedConfigSpace);\r
+ }\r
+ }\r
+ }\r
+\r
+ if ((ExtendedConfigSpace != NULL) && !ShellGetExecutionBreakFlag ()) {\r
+ //\r
+ // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)\r
+ //\r
+ ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r
+\r
+ DumpHex (\r
+ 2,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET,\r
+ ExtendedConfigSize,\r
+ ExtendedConfigSpace\r
+ );\r
+ }\r
+\r
//\r
// If "-i" appears in command line, interpret data in configuration space\r
//\r
if (ExplainData) {\r
- EnhancedDump = 0xFFFF;\r
- if (ShellCommandLineGetFlag(Package, L"-ec")) {\r
- Temp = ShellCommandLineGetValue(Package, L"-ec");\r
- ASSERT (Temp != NULL);\r
- EnhancedDump = (UINT16) ShellHexStrToUintn (Temp);\r
+ PciExplainPci (&ConfigSpace, Address, IoDev);\r
+ if ((ExtendedConfigSpace != NULL) && !ShellGetExecutionBreakFlag ()) {\r
+ PciExplainPciExpress (\r
+ (PCI_CAPABILITY_PCIEXP *) ((UINT8 *) &ConfigSpace + PcieCapabilityPtr),\r
+ ExtendedConfigSpace,\r
+ ExtendedCapability\r
+ );\r
}\r
- Status = PciExplainData (&ConfigSpace, Address, IoDev, EnhancedDump);\r
}\r
}\r
Done:\r
@param[in] ConfigSpace Data in PCI configuration space.\r
@param[in] Address Address used to access configuration space of this PCI device.\r
@param[in] IoDev Handle used to access configuration space of PCI device.\r
- @param[in] EnhancedDump The print format for the dump data.\r
-\r
- @retval EFI_SUCCESS The command completed successfully.\r
**/\r
-EFI_STATUS\r
-PciExplainData (\r
+VOID\r
+PciExplainPci (\r
IN PCI_CONFIG_SPACE *ConfigSpace,\r
IN UINT64 Address,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
- IN CONST UINT16 EnhancedDump\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
)\r
{\r
PCI_DEVICE_INDEPENDENT_REGION *Common;\r
PCI_HEADER_TYPE HeaderType;\r
- EFI_STATUS Status;\r
- UINT8 CapPtr;\r
\r
Common = &(ConfigSpace->Common);\r
\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
ShellPrintEx (-1, -1, L"\r\n");\r
-\r
- if (ShellGetExecutionBreakFlag()) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- //\r
- // Interpret remaining part of PCI configuration header depending on\r
- // HeaderType\r
- //\r
- CapPtr = 0;\r
- Status = EFI_SUCCESS;\r
- switch (HeaderType) {\r
- case PciDevice:\r
- Status = PciExplainDeviceData (\r
- &(ConfigSpace->NonCommon.Device),\r
- Address,\r
- IoDev\r
- );\r
- CapPtr = ConfigSpace->NonCommon.Device.CapabilityPtr;\r
- break;\r
-\r
- case PciP2pBridge:\r
- Status = PciExplainBridgeData (\r
- &(ConfigSpace->NonCommon.Bridge),\r
- Address,\r
- IoDev\r
- );\r
- CapPtr = ConfigSpace->NonCommon.Bridge.CapabilityPtr;\r
- break;\r
-\r
- case PciCardBusBridge:\r
- Status = PciExplainCardBusData (\r
- &(ConfigSpace->NonCommon.CardBus),\r
- Address,\r
- IoDev\r
- );\r
- CapPtr = ConfigSpace->NonCommon.CardBus.Cap_Ptr;\r
- break;\r
- case PciUndefined:\r
- default:\r
- break;\r
- }\r
- //\r
- // If Status bit4 is 1, dump or explain capability structure\r
- //\r
- if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {\r
- PciExplainCapabilityStruct (IoDev, Address, CapPtr, EnhancedDump);\r
- }\r
-\r
- return Status;\r
}\r
\r
/**\r
}\r
\r
/**\r
- Print each capability structure.\r
+ Locate capability register block per capability ID.\r
\r
- @param[in] IoDev The pointer to the deivce.\r
- @param[in] Address The address to start at.\r
- @param[in] CapPtr The offset from the address.\r
- @param[in] EnhancedDump The print format for the dump data.\r
+ @param[in] ConfigSpace Data in PCI configuration space.\r
+ @param[in] CapabilityId The capability ID.\r
\r
- @retval EFI_SUCCESS The operation was successful.\r
+ @return The offset of the register block per capability ID,\r
+ or 0 if the register block cannot be found.\r
**/\r
-EFI_STATUS\r
-PciExplainCapabilityStruct (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
- IN UINT64 Address,\r
- IN UINT8 CapPtr,\r
- IN CONST UINT16 EnhancedDump\r
+UINT8\r
+LocatePciCapability (\r
+ IN PCI_CONFIG_SPACE *ConfigSpace,\r
+ IN UINT8 CapabilityId\r
)\r
{\r
- UINT8 CapabilityPtr;\r
- UINT16 CapabilityEntry;\r
- UINT8 CapabilityID;\r
- UINT64 RegAddress;\r
-\r
- CapabilityPtr = CapPtr;\r
+ UINT8 CapabilityPtr;\r
+ EFI_PCI_CAPABILITY_HDR *CapabilityEntry;\r
\r
//\r
- // Go through the Capability list\r
+ // To check the cpability of this device supports\r
//\r
- while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
- RegAddress = Address + CapabilityPtr;\r
- IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);\r
+ if ((ConfigSpace->Common.Status & EFI_PCI_STATUS_CAPABILITY) == 0) {\r
+ return 0;\r
+ }\r
\r
- CapabilityID = (UINT8) CapabilityEntry;\r
+ switch ((PCI_HEADER_TYPE)(ConfigSpace->Common.HeaderType & 0x7f)) {\r
+ case PciDevice:\r
+ CapabilityPtr = ConfigSpace->NonCommon.Device.CapabilityPtr;\r
+ break;\r
+ case PciP2pBridge:\r
+ CapabilityPtr = ConfigSpace->NonCommon.Bridge.CapabilityPtr;\r
+ break;\r
+ case PciCardBusBridge:\r
+ CapabilityPtr = ConfigSpace->NonCommon.CardBus.Cap_Ptr;\r
+ break;\r
+ default:\r
+ return 0;\r
+ }\r
\r
- //\r
- // Explain PciExpress data\r
- //\r
- if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {\r
- PciExplainPciExpress (IoDev, Address, CapabilityPtr, EnhancedDump);\r
- return EFI_SUCCESS;\r
+ while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
+ CapabilityEntry = (EFI_PCI_CAPABILITY_HDR *) ((UINT8 *) ConfigSpace + CapabilityPtr);\r
+ if (CapabilityEntry->CapabilityID == CapabilityId) {\r
+ return CapabilityPtr;\r
}\r
+\r
//\r
- // Explain other capabilities here\r
+ // Certain PCI device may incorrectly have capability pointing to itself,\r
+ // break to avoid dead loop.\r
//\r
- CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r
+ if (CapabilityPtr == CapabilityEntry->NextItemPtr) {\r
+ break;\r
+ }\r
+\r
+ CapabilityPtr = CapabilityEntry->NextItemPtr;\r
}\r
\r
- return EFI_SUCCESS;\r
+ return 0;\r
}\r
\r
/**\r
Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL*)HeaderAddress;\r
\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL),\r
+ gShellDebug1HiiHandle,\r
Header->RootComplexLinkCapabilities,\r
Header->RootComplexLinkControl,\r
Header->RootComplexLinkStatus\r
- ); \r
+ );\r
DumpHex (\r
4,\r
EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING*)HeaderAddress;\r
\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_POWER), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_POWER),\r
+ gShellDebug1HiiHandle,\r
Header->DataSelect,\r
Header->Data,\r
Header->PowerBudgetCapability\r
- ); \r
+ );\r
DumpHex (\r
4,\r
EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
VectorSize = 0;\r
\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_ACS), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_ACS),\r
+ gShellDebug1HiiHandle,\r
Header->AcsCapability,\r
Header->AcsControl\r
- ); \r
+ );\r
if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header)) {\r
VectorSize = PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header);\r
if (VectorSize == 0) {\r
}\r
for (LoopCounter = 0 ; LoopCounter * 8 < VectorSize ; LoopCounter++) {\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_ACS2), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_ACS2),\r
+ gShellDebug1HiiHandle,\r
LoopCounter + 1,\r
Header->EgressControlVectorArray[LoopCounter]\r
- ); \r
+ );\r
}\r
}\r
DumpHex (\r
Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING*)HeaderAddress;\r
\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_LAT), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_LAT),\r
+ gShellDebug1HiiHandle,\r
Header->MaxSnoopLatency,\r
Header->MaxNoSnoopLatency\r
- ); \r
+ );\r
DumpHex (\r
4,\r
EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER*)HeaderAddress;\r
\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_SN), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_SN),\r
+ gShellDebug1HiiHandle,\r
Header->SerialNumber\r
- ); \r
+ );\r
DumpHex (\r
4,\r
EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER*)HeaderAddress;\r
\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_RCRB), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_RCRB),\r
+ gShellDebug1HiiHandle,\r
Header->VendorId,\r
Header->DeviceId,\r
Header->RcrbCapabilities,\r
Header->RcrbControl\r
- ); \r
+ );\r
DumpHex (\r
4,\r
EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC*)HeaderAddress;\r
\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_VEN), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_VEN),\r
+ gShellDebug1HiiHandle,\r
Header->VendorSpecificHeader\r
- ); \r
+ );\r
DumpHex (\r
4,\r
EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION*)HeaderAddress;\r
\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_ECEA), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_ECEA),\r
+ gShellDebug1HiiHandle,\r
Header->AssociationBitmap\r
- ); \r
+ );\r
DumpHex (\r
4,\r
EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY*)HeaderAddress;\r
\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_ARI), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_ARI),\r
+ gShellDebug1HiiHandle,\r
Header->AriCapability,\r
Header->AriControl\r
- ); \r
+ );\r
DumpHex (\r
4,\r
EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION*)HeaderAddress;\r
\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_DPA), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_DPA),\r
+ gShellDebug1HiiHandle,\r
Header->DpaCapability,\r
Header->DpaLatencyIndicator,\r
Header->DpaStatus,\r
Header->DpaControl\r
- ); \r
+ );\r
for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header) + 1 ; LinkCount++) {\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_DPA2), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_DPA2),\r
+ gShellDebug1HiiHandle,\r
LinkCount+1,\r
Header->DpaPowerAllocationArray[LinkCount]\r
);\r
Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION*)HeaderAddress;\r
\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR),\r
+ gShellDebug1HiiHandle,\r
Header->ElementSelfDescription\r
);\r
\r
for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header) ; LinkCount++) {\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2),\r
+ gShellDebug1HiiHandle,\r
LinkCount+1,\r
Header->LinkEntry[LinkCount]\r
);\r
Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING*)HeaderAddress;\r
\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_AER), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_AER),\r
+ gShellDebug1HiiHandle,\r
Header->UncorrectableErrorStatus,\r
Header->UncorrectableErrorMask,\r
Header->UncorrectableErrorSeverity,\r
Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST*)HeaderAddress;\r
\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST),\r
+ gShellDebug1HiiHandle,\r
Header->MultiCastCapability,\r
Header->MulticastControl,\r
Header->McBaseAddress,\r
Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY*)HeaderAddress;\r
\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE),\r
+ gShellDebug1HiiHandle,\r
Header->ExtendedVcCount,\r
Header->PortVcCapability1,\r
Header->PortVcCapability2,\r
for (ItemCount = 0 ; ItemCount < Header->ExtendedVcCount ; ItemCount++) {\r
CapabilityItem = &Header->Capability[ItemCount];\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM),\r
+ gShellDebug1HiiHandle,\r
ItemCount+1,\r
CapabilityItem->VcResourceCapability,\r
CapabilityItem->PortArbTableOffset,\r
DumpHex (\r
4,\r
EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
- sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC) + (Header->ExtendedVcCount - 1) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY)\r
+ + Header->ExtendedVcCount * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC),\r
(VOID *) (HeaderAddress)\r
);\r
\r
\r
for (ItemCount = 0 ; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) ; ItemCount++) {\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR),\r
+ gShellDebug1HiiHandle,\r
ItemCount+1,\r
Header->Capability[ItemCount].ResizableBarCapability,\r
Header->Capability[ItemCount].ResizableBarControl\r
Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH*)HeaderAddress;\r
\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_TPH), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_TPH),\r
+ gShellDebug1HiiHandle,\r
Header->TphRequesterCapability,\r
Header->TphRequesterControl\r
);\r
Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE*)HeaderAddress;\r
\r
ShellPrintHiiEx(\r
- -1, -1, NULL, \r
- STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY), \r
- gShellDebug1HiiHandle, \r
+ -1, -1, NULL,\r
+ STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY),\r
+ gShellDebug1HiiHandle,\r
Header->LinkControl3.Uint32,\r
Header->LaneErrorStatus\r
);\r
**/\r
EFI_STATUS\r
PrintPciExtendedCapabilityDetails(\r
- IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress, \r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCapPtr\r
)\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:\r
return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress, HeadersBaseAddress);\r
- case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID: \r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID:\r
//\r
// should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b\r
//\r
/**\r
Display Pcie device structure.\r
\r
- @param[in] IoDev The pointer to the root pci protocol.\r
- @param[in] Address The Address to start at.\r
- @param[in] CapabilityPtr The offset from the address to start.\r
- @param[in] EnhancedDump The print format for the dump data.\r
- \r
+ @param[in] PciExpressCap PCI Express capability buffer.\r
+ @param[in] ExtendedConfigSpace PCI Express extended configuration space.\r
+ @param[in] ExtendedCapability PCI Express extended capability ID to explain.\r
**/\r
-EFI_STATUS\r
+VOID\r
PciExplainPciExpress (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
- IN UINT64 Address,\r
- IN UINT8 CapabilityPtr,\r
- IN CONST UINT16 EnhancedDump\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap,\r
+ IN UINT8 *ExtendedConfigSpace,\r
+ IN CONST UINT16 ExtendedCapability\r
)\r
{\r
- PCI_CAPABILITY_PCIEXP PciExpressCap;\r
- EFI_STATUS Status;\r
- UINT64 CapRegAddress;\r
- UINT8 Bus;\r
- UINT8 Dev;\r
- UINT8 Func;\r
- UINT8 *ExRegBuffer;\r
- UINTN ExtendRegSize;\r
- UINT64 Pciex_Address;\r
UINT8 DevicePortType;\r
UINTN Index;\r
UINT8 *RegAddr;\r
UINTN RegValue;\r
PCI_EXP_EXT_HDR *ExtHdr;\r
\r
- CapRegAddress = Address + CapabilityPtr;\r
- IoDev->Pci.Read (\r
- IoDev,\r
- EfiPciWidthUint32,\r
- CapRegAddress,\r
- sizeof (PciExpressCap) / sizeof (UINT32),\r
- &PciExpressCap\r
- );\r
-\r
- DevicePortType = (UINT8)PciExpressCap.Capability.Bits.DevicePortType;\r
+ DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;\r
\r
ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");\r
\r
for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r
if (ShellGetExecutionBreakFlag()) {\r
- goto Done;\r
+ return;\r
}\r
- RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;\r
+ RegAddr = (UINT8 *) PciExpressCap + PcieExplainList[Index].Offset;\r
switch (PcieExplainList[Index].Width) {\r
case FieldWidthUINT8:\r
RegValue = *(UINT8 *) RegAddr;\r
//\r
if ((DevicePortType != PCIE_DEVICE_PORT_TYPE_ROOT_PORT &&\r
DevicePortType != PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT) ||\r
- !PciExpressCap.Capability.Bits.SlotImplemented) {\r
+ !PciExpressCap->Capability.Bits.SlotImplemented) {\r
continue;\r
}\r
break;\r
default:\r
break;\r
}\r
- PcieExplainList[Index].Func (&PciExpressCap);\r
+ PcieExplainList[Index].Func (PciExpressCap);\r
}\r
\r
- Bus = (UINT8) (RShiftU64 (Address, 24));\r
- Dev = (UINT8) (RShiftU64 (Address, 16));\r
- Func = (UINT8) (RShiftU64 (Address, 8));\r
-\r
- Pciex_Address = EFI_PCI_ADDRESS (Bus, Dev, Func, EFI_PCIE_CAPABILITY_BASE_OFFSET);\r
-\r
- ExtendRegSize = 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET;\r
-\r
- ExRegBuffer = (UINT8 *) AllocateZeroPool (ExtendRegSize);\r
-\r
- //\r
- // PciRootBridgeIo protocol should support pci express extend space IO\r
- // (Begins at offset EFI_PCIE_CAPABILITY_BASE_OFFSET)\r
- //\r
- Status = IoDev->Pci.Read (\r
- IoDev,\r
- EfiPciWidthUint32,\r
- Pciex_Address,\r
- (ExtendRegSize) / sizeof (UINT32),\r
- (VOID *) (ExRegBuffer)\r
- );\r
- if (EFI_ERROR (Status) || ExRegBuffer == NULL) {\r
- SHELL_FREE_NON_NULL(ExRegBuffer);\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- ExtHdr = (PCI_EXP_EXT_HDR*)ExRegBuffer;\r
+ ExtHdr = (PCI_EXP_EXT_HDR*)ExtendedConfigSpace;\r
while (ExtHdr->CapabilityId != 0 && ExtHdr->CapabilityVersion != 0) {\r
//\r
// Process this item\r
//\r
- if (EnhancedDump == 0xFFFF || EnhancedDump == ExtHdr->CapabilityId) {\r
+ if (ExtendedCapability == 0xFFFF || ExtendedCapability == ExtHdr->CapabilityId) {\r
//\r
// Print this item\r
//\r
- PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR*)ExRegBuffer, ExtHdr, &PciExpressCap);\r
+ PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR*)ExtendedConfigSpace, ExtHdr, PciExpressCap);\r
}\r
\r
//\r
// Advance to the next item if it exists\r
//\r
if (ExtHdr->NextCapabilityOffset != 0) {\r
- ExtHdr = (PCI_EXP_EXT_HDR*)((UINT8*)ExRegBuffer + ExtHdr->NextCapabilityOffset - EFI_PCIE_CAPABILITY_BASE_OFFSET);\r
+ ExtHdr = (PCI_EXP_EXT_HDR*)(ExtendedConfigSpace + ExtHdr->NextCapabilityOffset - EFI_PCIE_CAPABILITY_BASE_OFFSET);\r
} else {\r
break;\r
}\r
}\r
- SHELL_FREE_NON_NULL(ExRegBuffer);\r
-\r
-Done:\r
- return EFI_SUCCESS;\r
}\r
projects / mirror_edk2.git / blobdiff