/** @file\r
Main file for Pci shell Debug1 function.\r
\r
+ Copyright (c) 2013 Hewlett-Packard Development Company, L.P.\r
Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
bits 23:16 - Base Class Code\r
bits 15:8 - Sub-Class Code\r
bits 7:0 - Programming Interface\r
- @param[in,out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
+ @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
printable class strings corresponding to ClassCode. The\r
caller must not modify the strings that are pointed by\r
the fields in ClassStrings.\r
{\r
UINT32 ClassCode;\r
PCI_CLASS_STRINGS ClassStrings;\r
- CHAR16 OutputString[PCI_CLASS_STRING_LIMIT + 1];\r
\r
ClassCode = 0;\r
ClassCode |= ClassCodePtr[0];\r
\r
if (IncludePIF) {\r
//\r
- // Only print base class and sub class name\r
+ // Print base class, sub class, and programming inferface name\r
//\r
- ShellPrintEx(-1,-1, L"%s - %s - %s",\r
+ ShellPrintEx (-1, -1, L"%s - %s - %s",\r
ClassStrings.BaseClass,\r
ClassStrings.SubClass,\r
ClassStrings.PIFClass\r
\r
} else {\r
//\r
- // Print base class, sub class, and programming inferface name\r
+ // Only print base class and sub class name\r
//\r
- UnicodeSPrint (\r
- OutputString,\r
- PCI_CLASS_STRING_LIMIT * sizeof (CHAR16),\r
- L"%s - %s",\r
+ ShellPrintEx (-1, -1, L"%s - %s",\r
ClassStrings.BaseClass,\r
ClassStrings.SubClass\r
- );\r
-\r
- OutputString[PCI_CLASS_STRING_LIMIT] = 0;\r
- ShellPrintEx(-1,-1, L"%s", OutputString);\r
+ );\r
}\r
}\r
\r
It also moves the pointer backward a node, to get prepared to be called\r
again.\r
\r
- @param[in,out] Descriptors Points to current position of a serial of address space\r
- descriptors.\r
- @param[out] MinBus The lower range of bus number.\r
- @param[out] ManBus The upper range of bus number.\r
- @param[out] IsEnd Meet end of the serial of descriptors.\r
+ @param[in, out] Descriptors Points to current position of a serial of address space\r
+ descriptors.\r
+ @param[out] MinBus The lower range of bus number.\r
+ @param[out] MaxBus The upper range of bus number.\r
+ @param[out] IsEnd Meet end of the serial of descriptors.\r
\r
@retval EFI_SUCCESS The command completed successfully.\r
**/\r
/**\r
Explain the Base Address Register(Bar) in PCI configuration space.\r
\r
- @param[in] Bar Points to the Base Address Register intended to interpret.\r
- @param[in] Command Points to the register Command.\r
- @param[in] Address Address used to access configuration space of this PCI device.\r
- @param[in] IoDev Handle used to access configuration space of PCI device.\r
- @param[in,out] Index The Index.\r
+ @param[in] Bar Points to the Base Address Register intended to interpret.\r
+ @param[in] Command Points to the register Command.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+ @param[in, out] Index The Index.\r
\r
@retval EFI_SUCCESS The command completed successfully.\r
**/\r
LIST_ENTRY *Package;\r
CHAR16 *ProblemParam;\r
SHELL_STATUS ShellStatus;\r
- UINTN Size;\r
CONST CHAR16 *Temp;\r
+ UINT64 RetVal;\r
\r
ShellStatus = SHELL_SUCCESS;\r
Status = EFI_SUCCESS;\r
Address = 0;\r
- Size = 0;\r
IoDev = NULL;\r
HandleBuf = NULL;\r
Package = NULL;\r
\r
Temp = ShellCommandLineGetValue(Package, L"-s");\r
if (Temp != NULL) {\r
- Segment = (UINT16) ShellStrToUintn (Temp);\r
+ //\r
+ // Input converted to hexadecimal number.\r
+ //\r
+ if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
+ Segment = (UINT16) RetVal;\r
+ } else {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
}\r
\r
//\r
//\r
Temp = ShellCommandLineGetRawValue(Package, 1);\r
if (Temp != NULL) {\r
- Bus = (UINT16)ShellStrToUintn(Temp);\r
+ //\r
+ // Input converted to hexadecimal number.\r
+ //\r
+ if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
+ Bus = (UINT16) RetVal;\r
+ } else {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
+\r
if (Bus > MAX_BUS_NUMBER) {\r
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
}\r
Temp = ShellCommandLineGetRawValue(Package, 2);\r
if (Temp != NULL) {\r
- Device = (UINT16) ShellStrToUintn(Temp);\r
+ //\r
+ // Input converted to hexadecimal number.\r
+ //\r
+ if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
+ Device = (UINT16) RetVal;\r
+ } else {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
+\r
if (Device > MAX_DEVICE_NUMBER){\r
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
\r
Temp = ShellCommandLineGetRawValue(Package, 3);\r
if (Temp != NULL) {\r
- Func = (UINT16) ShellStrToUintn(Temp);\r
+ //\r
+ // Input converted to hexadecimal number.\r
+ //\r
+ if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
+ Func = (UINT16) RetVal;\r
+ } else {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
+\r
if (Func > MAX_FUNCTION_NUMBER){\r
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
if (EFI_ERROR (Status)) {\r
ShellPrintHiiEx(\r
-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,\r
- gShellDebug1HiiHandle,\r
Segment,\r
Bus\r
);\r
{\r
UINTN Index;\r
EFI_STATUS Status;\r
- BOOLEAN FoundInterface;\r
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
UINT16 MinBus;\r
UINT16 MaxBus;\r
BOOLEAN IsEnd;\r
\r
- FoundInterface = FALSE;\r
//\r
// Go through all handles, until the one meets the criteria is found\r
//\r
}\r
\r
if (MinBus <= Bus && MaxBus >= Bus) {\r
- FoundInterface = TRUE;\r
- break;\r
+ return EFI_SUCCESS;\r
}\r
}\r
}\r
\r
- if (FoundInterface) {\r
- return EFI_SUCCESS;\r
- } else {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
+ return EFI_NOT_FOUND;\r
}\r
\r
/**\r
It also moves the pointer backward a node, to get prepared to be called\r
again.\r
\r
- @param[in,out] Descriptors Points to current position of a serial of address space\r
- descriptors.\r
- @param[out] MinBus The lower range of bus number.\r
- @param[out] ManBus The upper range of bus number.\r
- @param[out] IsEnd Meet end of the serial of descriptors.\r
+ @param[in, out] Descriptors Points to current position of a serial of address space\r
+ descriptors.\r
+ @param[out] MinBus The lower range of bus number.\r
+ @param[out] MaxBus The upper range of bus number.\r
+ @param[out] IsEnd Meet end of the serial of descriptors.\r
\r
@retval EFI_SUCCESS The command completed successfully.\r
**/\r
\r
Common = &(ConfigSpace->Common);\r
\r
- Print (L"\n");\r
+ ShellPrintEx (-1, -1, L"\r\n");\r
\r
//\r
// Print Vendor Id and Device Id\r
//\r
// Print register Revision ID\r
//\r
- ShellPrintEx(-1, -1, L"/r/n");\r
+ ShellPrintEx(-1, -1, L"\r\n");\r
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r
INDEX_OF (&(Common->RevisionId)),\r
Common->RevisionId\r
//\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
- Print (L"\n");\r
+ ShellPrintEx (-1, -1, L"\r\n");\r
\r
if (ShellGetExecutionBreakFlag()) {\r
return EFI_SUCCESS;\r
);\r
CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r
break;\r
+ case PciUndefined:\r
+ default:\r
+ break;\r
}\r
//\r
// If Status bit4 is 1, dump or explain capability structure\r
if (!BarExist) {\r
BarExist = TRUE;\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r
- Print (L" --------------------------------------------------------------------------");\r
+ ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
}\r
\r
Status = PciExplainBar (\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
\r
} else {\r
- Print (L"\n --------------------------------------------------------------------------");\r
+ ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
}\r
\r
//\r
if (!BarExist) {\r
BarExist = TRUE;\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r
- Print (L" --------------------------------------------------------------------------");\r
+ ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
}\r
\r
Status = PciExplainBar (\r
if (!BarExist) {\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
} else {\r
- Print (L"\n --------------------------------------------------------------------------");\r
+ ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
}\r
\r
//\r
INDEX_OF (&(Bridge->SubordinateBus))\r
);\r
\r
- Print (L" ------------------------------------------------------\n");\r
+ ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r
// base and limit address are listed.\r
//\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r
- Print (L"----------------------------------------------------------------------\n");\r
+ ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
\r
//\r
// IO Base & Limit\r
/**\r
Explain the Base Address Register(Bar) in PCI configuration space.\r
\r
- @param[in] Bar Points to the Base Address Register intended to interpret.\r
- @param[in] Command Points to the register Command.\r
- @param[in] Address Address used to access configuration space of this PCI device.\r
- @param[in] IoDev Handle used to access configuration space of PCI device.\r
- @param[in,out] Index The Index.\r
+ @param[in] Bar Points to the Base Address Register intended to interpret.\r
+ @param[in] Command Points to the register Command.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+ @param[in, out] Index The Index.\r
\r
@retval EFI_SUCCESS The command completed successfully.\r
**/\r
} else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r
Bar64 = 0x0;\r
CopyMem (&Bar64, Bar, sizeof (UINT64));\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, RShiftU64 ((Bar64 & 0xfffffffffffffff0), 32));\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0));\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32) RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
IsBar32 = FALSE;\r
//\r
IsMem = FALSE;\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r
- Print (L"I/O ");\r
+ ShellPrintEx (-1, -1, L"I/O ");\r
}\r
\r
//\r
\r
OldBar64 = 0x0;\r
CopyMem (&OldBar64, Bar, sizeof (UINT64));\r
- NewBar64 = 0xffffffffffffffff;\r
+ NewBar64 = 0xffffffffffffffffULL;\r
\r
IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r
\r
if (IsMem) {\r
- NewBar64 = NewBar64 & 0xfffffffffffffff0;\r
+ NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;\r
NewBar64 = (~NewBar64) + 1;\r
\r
} else {\r
- NewBar64 = NewBar64 & 0xfffffffffffffffc;\r
+ NewBar64 = NewBar64 & 0xfffffffffffffffcULL;\r
NewBar64 = (~NewBar64) + 1;\r
NewBar64 = NewBar64 & 0x000000000000ffff;\r
}\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r
\r
} else {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, RShiftU64 (NewBar64, 32));\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) RShiftU64 (NewBar64, 32));\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r
- Print (L" ");\r
+ ShellPrintEx (-1, -1, L" ");\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_RSHIFT),\r
gShellDebug1HiiHandle,\r
- RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0) - 1), 32)\r
+ (UINT32) RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r
);\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0) - 1));\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r
\r
}\r
} else {\r
INDEX_OF (&(CardBus->SubordinateBusNumber))\r
);\r
\r
- Print (L" ------------------------------------------------------\n");\r
+ ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r
// Print Memory/Io ranges this cardbus bridge forwards\r
//\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r
- Print (L"----------------------------------------------------------------------\n");\r
+ ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_MEM_3),\r
INDEX_OF (&(CardBus->IoBase0)),\r
Io32Bit ? L" 32 bit" : L" 16 bit",\r
CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
- CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff) | 0x00000003\r
+ (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
);\r
\r
Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r
INDEX_OF (&(CardBus->IoBase1)),\r
Io32Bit ? L" 32 bit" : L" 16 bit",\r
CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
- CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff) | 0x00000003\r
+ (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
);\r
\r
//\r
CHAR16 *DevicePortType;\r
\r
PcieCapReg = PciExpressCap->PcieCapReg;\r
- Print (\r
- L" Capability Version(3:0): %E0x%04x%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Capability Version(3:0): %E0x%04x%N\r\n",\r
PCIE_CAP_VERSION (PcieCapReg)\r
);\r
if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {\r
} else {\r
DevicePortType = L"Unknown Type";\r
}\r
- Print (\r
- L" Device/PortType(7:4): %E%s%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Device/PortType(7:4): %E%s%N\r\n",\r
DevicePortType\r
);\r
//\r
//\r
if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||\r
PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {\r
- Print (\r
- L" Slot Implemented(8): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Slot Implemented(8): %E%d%N\r\n",\r
PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)\r
);\r
}\r
- Print (\r
- L" Interrupt Message Number(13:9): %E0x%05x%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Interrupt Message Number(13:9): %E0x%05x%N\r\n",\r
PCIE_CAP_INT_MSG_NUM (PcieCapReg)\r
);\r
return EFI_SUCCESS;\r
PcieCapReg = PciExpressCap->PcieCapReg;\r
PcieDeviceCap = PciExpressCap->PcieDeviceCap;\r
DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);\r
- Print (L" Max_Payload_Size Supported(2:0): ");\r
+ ShellPrintEx (-1, -1, L" Max_Payload_Size Supported(2:0): ");\r
if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {\r
- Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r
+ ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r
} else {\r
- Print (L"%EUnknown%N\n");\r
+ ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
}\r
- Print (\r
- L" Phantom Functions Supported(4:3): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Phantom Functions Supported(4:3): %E%d%N\r\n",\r
PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)\r
);\r
- Print (\r
- L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",\r
PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5\r
);\r
//\r
if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);\r
L1Latency = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);\r
- Print (L" Endpoint L0s Acceptable Latency(8:6): ");\r
+ ShellPrintEx (-1, -1, L" Endpoint L0s Acceptable Latency(8:6): ");\r
if (L0sLatency < 4) {\r
- Print (L"%EMaximum of %d ns%N\n", 1 << (L0sLatency + 6));\r
+ ShellPrintEx (-1, -1, L"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency + 6));\r
} else {\r
if (L0sLatency < 7) {\r
- Print (L"%EMaximum of %d us%N\n", 1 << (L0sLatency - 3));\r
+ ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L0sLatency - 3));\r
} else {\r
- Print (L"%ENo limit%N\n");\r
+ ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
}\r
}\r
- Print (L" Endpoint L1 Acceptable Latency(11:9): ");\r
+ ShellPrintEx (-1, -1, L" Endpoint L1 Acceptable Latency(11:9): ");\r
if (L1Latency < 7) {\r
- Print (L"%EMaximum of %d us%N\n", 1 << (L1Latency + 1));\r
+ ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L1Latency + 1));\r
} else {\r
- Print (L"%ENo limit%N\n");\r
+ ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
}\r
}\r
- Print (\r
- L" Role-based Error Reporting(15): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Role-based Error Reporting(15): %E%d%N\r\n",\r
PCIE_CAP_ERR_REPORTING (PcieDeviceCap)\r
);\r
//\r
// b) Captured Slot Power Scale\r
//\r
if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {\r
- Print (\r
- L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",\r
PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)\r
);\r
- Print (\r
- L" Captured Slot Power Limit Scale(27:26): %E%s%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",\r
SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]\r
);\r
}\r
// Function Level Reset Capability is only valid for Endpoint\r
//\r
if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
- Print (\r
- L" Function Level Reset Capability(28): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Function Level Reset Capability(28): %E%d%N\r\n",\r
PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)\r
);\r
}\r
\r
PcieCapReg = PciExpressCap->PcieCapReg;\r
PcieDeviceControl = PciExpressCap->DeviceControl;\r
- Print (\r
- L" Correctable Error Reporting Enable(0): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Correctable Error Reporting Enable(0): %E%d%N\r\n",\r
PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
);\r
- Print (\r
- L" Non-Fatal Error Reporting Enable(1): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",\r
PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
);\r
- Print (\r
- L" Fatal Error Reporting Enable(2): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Fatal Error Reporting Enable(2): %E%d%N\r\n",\r
PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
);\r
- Print (\r
- L" Unsupported Request Reporting Enable(3): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Unsupported Request Reporting Enable(3): %E%d%N\r\n",\r
PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)\r
);\r
- Print (\r
- L" Enable Relaxed Ordering(4): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Enable Relaxed Ordering(4): %E%d%N\r\n",\r
PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)\r
);\r
- Print (L" Max_Payload_Size(7:5): ");\r
+ ShellPrintEx (-1, -1, L" Max_Payload_Size(7:5): ");\r
if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {\r
- Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r
+ ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r
} else {\r
- Print (L"%EUnknown%N\n");\r
+ ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
}\r
- Print (\r
- L" Extended Tag Field Enable(8): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Extended Tag Field Enable(8): %E%d%N\r\n",\r
PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)\r
);\r
- Print (\r
- L" Phantom Functions Enable(9): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Phantom Functions Enable(9): %E%d%N\r\n",\r
PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)\r
);\r
- Print (\r
- L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",\r
PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)\r
);\r
- Print (\r
- L" Enable No Snoop(11): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Enable No Snoop(11): %E%d%N\r\n",\r
PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)\r
);\r
- Print (L" Max_Read_Request_Size(14:12): ");\r
+ ShellPrintEx (-1, -1, L" Max_Read_Request_Size(14:12): ");\r
if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {\r
- Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r
+ ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r
} else {\r
- Print (L"%EUnknown%N\n");\r
+ ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
}\r
//\r
// Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r
//\r
if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {\r
- Print (\r
- L" Bridge Configuration Retry Enable(15): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Bridge Configuration Retry Enable(15): %E%d%N\r\n",\r
PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)\r
);\r
}\r
UINT16 PcieDeviceStatus;\r
\r
PcieDeviceStatus = PciExpressCap->DeviceStatus;\r
- Print (\r
- L" Correctable Error Detected(0): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Correctable Error Detected(0): %E%d%N\r\n",\r
PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)\r
);\r
- Print (\r
- L" Non-Fatal Error Detected(1): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Non-Fatal Error Detected(1): %E%d%N\r\n",\r
PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)\r
);\r
- Print (\r
- L" Fatal Error Detected(2): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Fatal Error Detected(2): %E%d%N\r\n",\r
PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)\r
);\r
- Print (\r
- L" Unsupported Request Detected(3): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Unsupported Request Detected(3): %E%d%N\r\n",\r
PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)\r
);\r
- Print (\r
- L" AUX Power Detected(4): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" AUX Power Detected(4): %E%d%N\r\n",\r
PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)\r
);\r
- Print (\r
- L" Transactions Pending(5): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Transactions Pending(5): %E%d%N\r\n",\r
PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)\r
);\r
return EFI_SUCCESS;\r
)\r
{\r
UINT32 PcieLinkCap;\r
- CHAR16 *SupLinkSpeeds;\r
+ CHAR16 *MaxLinkSpeed;\r
CHAR16 *AspmValue;\r
\r
PcieLinkCap = PciExpressCap->LinkCap;\r
- switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap)) {\r
+ switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap)) {\r
case 1:\r
- SupLinkSpeeds = L"2.5 GT/s";\r
+ MaxLinkSpeed = L"2.5 GT/s";\r
break;\r
case 2:\r
- SupLinkSpeeds = L"5.0 GT/s and 2.5 GT/s";\r
+ MaxLinkSpeed = L"5.0 GT/s";\r
+ break;\r
+ case 3:\r
+ MaxLinkSpeed = L"8.0 GT/s";\r
break;\r
default:\r
- SupLinkSpeeds = L"Unknown";\r
+ MaxLinkSpeed = L"Unknown";\r
break;\r
}\r
- Print (\r
- L" Supported Link Speeds(3:0): %E%s supported%N\n",\r
- SupLinkSpeeds\r
+ ShellPrintEx (-1, -1,\r
+ L" Maximum Link Speed(3:0): %E%s%N\r\n",\r
+ MaxLinkSpeed\r
);\r
- Print (\r
- L" Maximum Link Width(9:4): %Ex%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Maximum Link Width(9:4): %Ex%d%N\r\n",\r
PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r
);\r
switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
+ case 0:\r
+ AspmValue = L"Not";\r
+ break;\r
case 1:\r
- AspmValue = L"L0s Entry";\r
+ AspmValue = L"L0s";\r
+ break;\r
+ case 2:\r
+ AspmValue = L"L1";\r
break;\r
case 3:\r
AspmValue = L"L0s and L1";\r
AspmValue = L"Reserved";\r
break;\r
}\r
- Print (\r
- L" Active State Power Management Support(11:10): %E%s Supported%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Active State Power Management Support(11:10): %E%s Supported%N\r\n",\r
AspmValue\r
);\r
- Print (\r
- L" L0s Exit Latency(14:12): %E%s%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" L0s Exit Latency(14:12): %E%s%N\r\n",\r
L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
);\r
- Print (\r
- L" L1 Exit Latency(17:15): %E%s%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" L1 Exit Latency(17:15): %E%s%N\r\n",\r
L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
);\r
- Print (\r
- L" Clock Power Management(18): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Clock Power Management(18): %E%d%N\r\n",\r
PCIE_CAP_CLOCK_PM (PcieLinkCap)\r
);\r
- Print (\r
- L" Surprise Down Error Reporting Capable(19): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",\r
PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)\r
);\r
- Print (\r
- L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",\r
PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)\r
);\r
- Print (\r
- L" Link Bandwidth Notification Capability(21): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Bandwidth Notification Capability(21): %E%d%N\r\n",\r
PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)\r
);\r
- Print (\r
- L" Port Number(31:24): %E0x%02x%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Port Number(31:24): %E0x%02x%N\r\n",\r
PCIE_CAP_PORT_NUMBER (PcieLinkCap)\r
);\r
return EFI_SUCCESS;\r
\r
PcieLinkControl = PciExpressCap->LinkControl;\r
DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);\r
- Print (\r
- L" Active State Power Management Control(1:0): %E%s%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Active State Power Management Control(1:0): %E%s%N\r\n",\r
ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]\r
);\r
//\r
// RCB is not applicable to switches\r
//\r
if (!IS_PCIE_SWITCH(DevicePortType)) {\r
- Print (\r
- L" Read Completion Boundary (RCB)(3): %E%d byte%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",\r
1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)\r
);\r
}\r
if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r
DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&\r
DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {\r
- Print (\r
- L" Link Disable(4): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Disable(4): %E%d%N\r\n",\r
PCIE_CAP_LINK_DISABLE (PcieLinkControl)\r
);\r
}\r
- Print (\r
- L" Common Clock Configuration(6): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Common Clock Configuration(6): %E%d%N\r\n",\r
PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)\r
);\r
- Print (\r
- L" Extended Synch(7): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Extended Synch(7): %E%d%N\r\n",\r
PCIE_CAP_EXT_SYNC (PcieLinkControl)\r
);\r
- Print (\r
- L" Enable Clock Power Management(8): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Enable Clock Power Management(8): %E%d%N\r\n",\r
PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)\r
);\r
- Print (\r
- L" Hardware Autonomous Width Disable(9): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Hardware Autonomous Width Disable(9): %E%d%N\r\n",\r
PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)\r
);\r
- Print (\r
- L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",\r
PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)\r
);\r
- Print (\r
- L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",\r
PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)\r
);\r
return EFI_SUCCESS;\r
)\r
{\r
UINT16 PcieLinkStatus;\r
- CHAR16 *SupLinkSpeeds;\r
+ CHAR16 *CurLinkSpeed;\r
\r
PcieLinkStatus = PciExpressCap->LinkStatus;\r
switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r
case 1:\r
- SupLinkSpeeds = L"2.5 GT/s";\r
+ CurLinkSpeed = L"2.5 GT/s";\r
break;\r
case 2:\r
- SupLinkSpeeds = L"5.0 GT/s";\r
+ CurLinkSpeed = L"5.0 GT/s";\r
+ break;\r
+ case 3:\r
+ CurLinkSpeed = L"8.0 GT/s";\r
break;\r
default:\r
- SupLinkSpeeds = L"Reserved";\r
+ CurLinkSpeed = L"Reserved";\r
break;\r
}\r
- Print (\r
- L" Current Link Speed(3:0): %E%s%N\n",\r
- SupLinkSpeeds\r
+ ShellPrintEx (-1, -1,\r
+ L" Current Link Speed(3:0): %E%s%N\r\n",\r
+ CurLinkSpeed\r
);\r
- Print (\r
- L" Negotiated Link Width(9:4): %Ex%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Negotiated Link Width(9:4): %Ex%d%N\r\n",\r
PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)\r
);\r
- Print (\r
- L" Link Training(11): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Training(11): %E%d%N\r\n",\r
PCIE_CAP_LINK_TRAINING (PcieLinkStatus)\r
);\r
- Print (\r
- L" Slot Clock Configuration(12): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Slot Clock Configuration(12): %E%d%N\r\n",\r
PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)\r
);\r
- Print (\r
- L" Data Link Layer Link Active(13): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Data Link Layer Link Active(13): %E%d%N\r\n",\r
PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)\r
);\r
- Print (\r
- L" Link Bandwidth Management Status(14): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Bandwidth Management Status(14): %E%d%N\r\n",\r
PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)\r
);\r
- Print (\r
- L" Link Autonomous Bandwidth Status(15): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",\r
PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)\r
);\r
return EFI_SUCCESS;\r
\r
PcieSlotCap = PciExpressCap->SlotCap;\r
\r
- Print (\r
- L" Attention Button Present(0): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Attention Button Present(0): %E%d%N\r\n",\r
PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)\r
);\r
- Print (\r
- L" Power Controller Present(1): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Power Controller Present(1): %E%d%N\r\n",\r
PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)\r
);\r
- Print (\r
- L" MRL Sensor Present(2): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" MRL Sensor Present(2): %E%d%N\r\n",\r
PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)\r
);\r
- Print (\r
- L" Attention Indicator Present(3): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Attention Indicator Present(3): %E%d%N\r\n",\r
PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)\r
);\r
- Print (\r
- L" Power Indicator Present(4): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Power Indicator Present(4): %E%d%N\r\n",\r
PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)\r
);\r
- Print (\r
- L" Hot-Plug Surprise(5): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Hot-Plug Surprise(5): %E%d%N\r\n",\r
PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)\r
);\r
- Print (\r
- L" Hot-Plug Capable(6): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Hot-Plug Capable(6): %E%d%N\r\n",\r
PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)\r
);\r
- Print (\r
- L" Slot Power Limit Value(14:7): %E0x%02x%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",\r
PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)\r
);\r
- Print (\r
- L" Slot Power Limit Scale(16:15): %E%s%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Slot Power Limit Scale(16:15): %E%s%N\r\n",\r
SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]\r
);\r
- Print (\r
- L" Electromechanical Interlock Present(17): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Electromechanical Interlock Present(17): %E%d%N\r\n",\r
PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)\r
);\r
- Print (\r
- L" No Command Completed Support(18): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" No Command Completed Support(18): %E%d%N\r\n",\r
PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)\r
);\r
- Print (\r
- L" Physical Slot Number(31:19): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Physical Slot Number(31:19): %E%d%N\r\n",\r
PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)\r
);\r
\r
UINT16 PcieSlotControl;\r
\r
PcieSlotControl = PciExpressCap->SlotControl;\r
- Print (\r
- L" Attention Button Pressed Enable(0): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Attention Button Pressed Enable(0): %E%d%N\r\n",\r
PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)\r
);\r
- Print (\r
- L" Power Fault Detected Enable(1): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Power Fault Detected Enable(1): %E%d%N\r\n",\r
PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)\r
);\r
- Print (\r
- L" MRL Sensor Changed Enable(2): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" MRL Sensor Changed Enable(2): %E%d%N\r\n",\r
PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)\r
);\r
- Print (\r
- L" Presence Detect Changed Enable(3): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Presence Detect Changed Enable(3): %E%d%N\r\n",\r
PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)\r
);\r
- Print (\r
- L" Command Completed Interrupt Enable(4): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Command Completed Interrupt Enable(4): %E%d%N\r\n",\r
PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)\r
);\r
- Print (\r
- L" Hot-Plug Interrupt Enable(5): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",\r
PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)\r
);\r
- Print (\r
- L" Attention Indicator Control(7:6): %E%s%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Attention Indicator Control(7:6): %E%s%N\r\n",\r
IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]\r
);\r
- Print (\r
- L" Power Indicator Control(9:8): %E%s%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Power Indicator Control(9:8): %E%s%N\r\n",\r
IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]\r
);\r
- Print (L" Power Controller Control(10): %EPower ");\r
+ ShellPrintEx (-1, -1, L" Power Controller Control(10): %EPower ");\r
if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {\r
- Print (L"Off%N\n");\r
+ ShellPrintEx (-1, -1, L"Off%N\r\n");\r
} else {\r
- Print (L"On%N\n");\r
+ ShellPrintEx (-1, -1, L"On%N\r\n");\r
}\r
- Print (\r
- L" Electromechanical Interlock Control(11): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Electromechanical Interlock Control(11): %E%d%N\r\n",\r
PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)\r
);\r
- Print (\r
- L" Data Link Layer State Changed Enable(12): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Data Link Layer State Changed Enable(12): %E%d%N\r\n",\r
PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)\r
);\r
return EFI_SUCCESS;\r
\r
PcieSlotStatus = PciExpressCap->SlotStatus;\r
\r
- Print (\r
- L" Attention Button Pressed(0): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Attention Button Pressed(0): %E%d%N\r\n",\r
PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)\r
);\r
- Print (\r
- L" Power Fault Detected(1): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Power Fault Detected(1): %E%d%N\r\n",\r
PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)\r
);\r
- Print (\r
- L" MRL Sensor Changed(2): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" MRL Sensor Changed(2): %E%d%N\r\n",\r
PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)\r
);\r
- Print (\r
- L" Presence Detect Changed(3): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Presence Detect Changed(3): %E%d%N\r\n",\r
PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)\r
);\r
- Print (\r
- L" Command Completed(4): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Command Completed(4): %E%d%N\r\n",\r
PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)\r
);\r
- Print (L" MRL Sensor State(5): %EMRL ");\r
+ ShellPrintEx (-1, -1, L" MRL Sensor State(5): %EMRL ");\r
if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {\r
- Print (L" Opened%N\n");\r
+ ShellPrintEx (-1, -1, L" Opened%N\r\n");\r
} else {\r
- Print (L" Closed%N\n");\r
+ ShellPrintEx (-1, -1, L" Closed%N\r\n");\r
}\r
- Print (L" Presence Detect State(6): ");\r
+ ShellPrintEx (-1, -1, L" Presence Detect State(6): ");\r
if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {\r
- Print (L"%ECard Present in slot%N\n");\r
+ ShellPrintEx (-1, -1, L"%ECard Present in slot%N\r\n");\r
} else {\r
- Print (L"%ESlot Empty%N\n");\r
+ ShellPrintEx (-1, -1, L"%ESlot Empty%N\r\n");\r
}\r
- Print (L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
+ ShellPrintEx (-1, -1, L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {\r
- Print (L"Engaged%N\n");\r
+ ShellPrintEx (-1, -1, L"Engaged%N\r\n");\r
} else {\r
- Print (L"Disengaged%N\n");\r
+ ShellPrintEx (-1, -1, L"Disengaged%N\r\n");\r
}\r
- Print (\r
- L" Data Link Layer State Changed(8): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Data Link Layer State Changed(8): %E%d%N\r\n",\r
PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)\r
);\r
return EFI_SUCCESS;\r
\r
PcieRootControl = PciExpressCap->RootControl;\r
\r
- Print (\r
- L" System Error on Correctable Error Enable(0): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" System Error on Correctable Error Enable(0): %E%d%N\r\n",\r
PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)\r
);\r
- Print (\r
- L" System Error on Non-Fatal Error Enable(1): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",\r
PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)\r
);\r
- Print (\r
- L" System Error on Fatal Error Enable(2): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" System Error on Fatal Error Enable(2): %E%d%N\r\n",\r
PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)\r
);\r
- Print (\r
- L" PME Interrupt Enable(3): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" PME Interrupt Enable(3): %E%d%N\r\n",\r
PCIE_CAP_PME_INT_ENABLE (PcieRootControl)\r
);\r
- Print (\r
- L" CRS Software Visibility Enable(4): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" CRS Software Visibility Enable(4): %E%d%N\r\n",\r
PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)\r
);\r
\r
\r
PcieRootCap = PciExpressCap->RsvdP;\r
\r
- Print (\r
- L" CRS Software Visibility(0): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" CRS Software Visibility(0): %E%d%N\r\n",\r
PCIE_CAP_CRS_SW_VIS (PcieRootCap)\r
);\r
\r
\r
PcieRootStatus = PciExpressCap->RootStatus;\r
\r
- Print (\r
- L" PME Requester ID(15:0): %E0x%04x%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" PME Requester ID(15:0): %E0x%04x%N\r\n",\r
PCIE_CAP_PME_REQ_ID (PcieRootStatus)\r
);\r
- Print (\r
- L" PME Status(16): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" PME Status(16): %E%d%N\r\n",\r
PCIE_CAP_PME_STATUS (PcieRootStatus)\r
);\r
- Print (\r
- L" PME Pending(17): %E%d%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" PME Pending(17): %E%d%N\r\n",\r
PCIE_CAP_PME_PENDING (PcieRootStatus)\r
);\r
return EFI_SUCCESS;\r
\r
DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);\r
\r
- Print (L"\nPci Express device capability structure:\n");\r
+ ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");\r
\r
for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r
if (ShellGetExecutionBreakFlag()) {\r
//\r
// Start outputing PciEx extend space( 0xFF-0xFFF)\r
//\r
- Print (L"\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\n\n");\r
+ ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r
\r
- DumpHex (\r
- 2,\r
- 0x100,\r
- ExtendRegSize,\r
- (VOID *) (ExRegBuffer)\r
- );\r
+ if (ExRegBuffer != NULL) {\r
+ DumpHex (\r
+ 2,\r
+ 0x100,\r
+ ExtendRegSize,\r
+ (VOID *) (ExRegBuffer)\r
+ );\r
\r
- FreePool ((VOID *) ExRegBuffer);\r
+ FreePool ((VOID *) ExRegBuffer);\r
+ }\r
\r
Done:\r
return EFI_SUCCESS;\r
projects / mirror_edk2.git / blobdiff