(((PcieDeviceCap) >> 3) & 0x3)\r
#define PCIE_CAP_EXTENDED_TAG(PcieDeviceCap) \\r
(((PcieDeviceCap) >> 5) & 0x1)\r
-#define PCIE_CAP_L0sLatency(PcieDeviceCap) \\r
+#define PCIE_CAP_L0SLATENCY(PcieDeviceCap) \\r
(((PcieDeviceCap) >> 6) & 0x7)\r
-#define PCIE_CAP_L1Latency(PcieDeviceCap) \\r
+#define PCIE_CAP_L1LATENCY(PcieDeviceCap) \\r
(((PcieDeviceCap) >> 9) & 0x7)\r
#define PCIE_CAP_ERR_REPORTING(PcieDeviceCap) \\r
(((PcieDeviceCap) >> 15) & 0x1)\r
(((PcieLinkCap) >> 4) & 0x3f)\r
#define PCIE_CAP_ASPM_SUPPORT(PcieLinkCap) \\r
(((PcieLinkCap) >> 10) & 0x3)\r
-#define PCIE_CAP_L0s_LATENCY(PcieLinkCap) \\r
+#define PCIE_CAP_L0S_LATENCY(PcieLinkCap) \\r
(((PcieLinkCap) >> 12) & 0x7)\r
#define PCIE_CAP_L1_LATENCY(PcieLinkCap) \\r
(((PcieLinkCap) >> 15) & 0x7)\r
UINT8 CacheLineSize;\r
UINT8 PrimaryLatencyTimer;\r
UINT8 HeaderType;\r
- UINT8 BIST;\r
+ UINT8 Bist;\r
\r
} PCI_COMMON_HEADER;\r
\r
UINT32 Data[46];\r
} PCI_CARDBUS_DATA;\r
\r
+typedef union {\r
+ PCI_DEVICE_HEADER Device;\r
+ PCI_BRIDGE_HEADER Bridge;\r
+ PCI_CARDBUS_HEADER CardBus;\r
+} NON_COMMON_UNION;\r
+\r
typedef struct {\r
PCI_COMMON_HEADER Common;\r
- union {\r
- PCI_DEVICE_HEADER Device;\r
- PCI_BRIDGE_HEADER Bridge;\r
- PCI_CARDBUS_HEADER CardBus;\r
- } NonCommon;\r
+ NON_COMMON_UNION NonCommon;\r
UINT32 Data[48];\r
} PCI_CONFIG_SPACE;\r
\r