BOOLEAN InterruptState = FALSE;\r
EFI_HANDLE mCpuHandle = NULL;\r
BOOLEAN mIsFlushingGCD;\r
-UINT64 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;\r
-UINT64 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;\r
+UINT64 mValidMtrrAddressMask;\r
+UINT64 mValidMtrrBitsMask;\r
+UINT64 mTimerPeriod = 0;\r
\r
FIXED_MTRR mFixedMtrrTable[] = {\r
{\r
- MTRR_LIB_IA32_MTRR_FIX64K_00000,\r
+ MSR_IA32_MTRR_FIX64K_00000,\r
0,\r
0x10000\r
},\r
{\r
- MTRR_LIB_IA32_MTRR_FIX16K_80000,\r
+ MSR_IA32_MTRR_FIX16K_80000,\r
0x80000,\r
0x4000\r
},\r
{\r
- MTRR_LIB_IA32_MTRR_FIX16K_A0000,\r
+ MSR_IA32_MTRR_FIX16K_A0000,\r
0xA0000,\r
0x4000\r
},\r
{\r
- MTRR_LIB_IA32_MTRR_FIX4K_C0000,\r
+ MSR_IA32_MTRR_FIX4K_C0000,\r
0xC0000,\r
0x1000\r
},\r
{\r
- MTRR_LIB_IA32_MTRR_FIX4K_C8000,\r
+ MSR_IA32_MTRR_FIX4K_C8000,\r
0xC8000,\r
0x1000\r
},\r
{\r
- MTRR_LIB_IA32_MTRR_FIX4K_D0000,\r
+ MSR_IA32_MTRR_FIX4K_D0000,\r
0xD0000,\r
0x1000\r
},\r
{\r
- MTRR_LIB_IA32_MTRR_FIX4K_D8000,\r
+ MSR_IA32_MTRR_FIX4K_D8000,\r
0xD8000,\r
0x1000\r
},\r
{\r
- MTRR_LIB_IA32_MTRR_FIX4K_E0000,\r
+ MSR_IA32_MTRR_FIX4K_E0000,\r
0xE0000,\r
0x1000\r
},\r
{\r
- MTRR_LIB_IA32_MTRR_FIX4K_E8000,\r
+ MSR_IA32_MTRR_FIX4K_E8000,\r
0xE8000,\r
0x1000\r
},\r
{\r
- MTRR_LIB_IA32_MTRR_FIX4K_F0000,\r
+ MSR_IA32_MTRR_FIX4K_F0000,\r
0xF0000,\r
0x1000\r
},\r
{\r
- MTRR_LIB_IA32_MTRR_FIX4K_F8000,\r
+ MSR_IA32_MTRR_FIX4K_F8000,\r
0xF8000,\r
0x1000\r
},\r
OUT UINT64 *TimerPeriod OPTIONAL\r
)\r
{\r
+ UINT64 BeginValue;\r
+ UINT64 EndValue;\r
+\r
if (TimerValue == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
*TimerValue = AsmReadTsc ();\r
\r
if (TimerPeriod != NULL) {\r
+ if (mTimerPeriod == 0) {\r
+ //\r
+ // Read time stamp counter before and after delay of 100 microseconds\r
//\r
- // BugBug: Hard coded. Don't know how to do this generically\r
+ BeginValue = AsmReadTsc ();\r
+ MicroSecondDelay (100);\r
+ EndValue = AsmReadTsc ();\r
//\r
- *TimerPeriod = 1000000000;\r
+ // Calculate the actual frequency\r
+ //\r
+ mTimerPeriod = DivU64x64Remainder (\r
+ MultU64x32 (\r
+ 1000 * 1000 * 1000,\r
+ 100\r
+ ),\r
+ EndValue - BeginValue,\r
+ NULL\r
+ );\r
+ }\r
+ *TimerPeriod = mTimerPeriod;\r
}\r
\r
return EFI_SUCCESS;\r
// to avoid unnecessary computing.\r
//\r
if (mIsFlushingGCD) {\r
- DEBUG((EFI_D_INFO, " Flushing GCD\n"));\r
+ DEBUG((DEBUG_INFO, " Flushing GCD\n"));\r
return EFI_SUCCESS;\r
}\r
\r
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
\r
PhysicalAddressBits = (UINT8) RegEax;\r
-\r
- mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;\r
- mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;\r
} else {\r
- mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;\r
- mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;\r
+ PhysicalAddressBits = 36;\r
}\r
+\r
+ mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;\r
+ mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;\r
}\r
\r
/**\r
IntersectionBase, IntersectionEnd - IntersectionBase,\r
Capabilities);\r
\r
- DEBUG ((EFI_ERROR (Status) ? EFI_D_ERROR : EFI_D_VERBOSE,\r
+ DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,\r
"%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,\r
IntersectionBase, IntersectionEnd, Status));\r
return Status;\r
}\r
\r
- DEBUG ((EFI_D_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "\r
+ DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "\r
"with aperture [%Lx, %Lx) cap %Lx\n", gEfiCallerBaseName, __FUNCTION__,\r
Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,\r
(UINT32)Descriptor->GcdMemoryType, Descriptor->Capabilities,\r
\r
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n",\r
+ DEBUG ((DEBUG_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n",\r
gEfiCallerBaseName, __FUNCTION__, Status));\r
return Status;\r
}\r
return Status;\r
}\r
\r
+/**\r
+ Add and allocate CPU local APIC memory mapped space. \r
+\r
+ @param[in]ImageHandle Image handle this driver.\r
+\r
+**/\r
+VOID\r
+AddLocalApicMemorySpace (\r
+ IN EFI_HANDLE ImageHandle\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS BaseAddress;\r
+\r
+ BaseAddress = (EFI_PHYSICAL_ADDRESS) GetLocalApicBaseAddress();\r
+ Status = AddMemoryMappedIoSpace (BaseAddress, SIZE_4KB, EFI_MEMORY_UC);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Try to allocate APIC memory mapped space, does not check return \r
+ // status because it may be allocated by other driver, or DXE Core if\r
+ // this range is built into Memory Allocation HOB.\r
+ //\r
+ Status = gDS->AllocateMemorySpace (\r
+ EfiGcdAllocateAddress,\r
+ EfiGcdMemoryTypeMemoryMappedIo,\r
+ 0,\r
+ SIZE_4KB,\r
+ &BaseAddress,\r
+ ImageHandle,\r
+ NULL\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_INFO, "%a: %a: AllocateMemorySpace() Status - %r\n",\r
+ gEfiCallerBaseName, __FUNCTION__, Status));\r
+ }\r
+}\r
+\r
/**\r
Initialize the state information for the CPU Architectural Protocol.\r
\r
//\r
InitInterruptDescriptorTable ();\r
\r
- //\r
- // Enable the local APIC for Virtual Wire Mode.\r
- //\r
- ProgramVirtualWireMode ();\r
-\r
//\r
// Install CPU Architectural Protocol\r
//\r
//\r
RefreshGcdMemoryAttributes ();\r
\r
+ //\r
+ // Add and allocate local APIC memory mapped space\r
+ //\r
+ AddLocalApicMemorySpace (ImageHandle);\r
+\r
//\r
// Setup a callback for idle events\r
//\r