/** @file\r
Definitions for CPU S3 data.\r
\r
-Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
// Element of register table entry\r
//\r
typedef struct {\r
- REGISTER_TYPE RegisterType;\r
- UINT32 Index;\r
- UINT8 ValidBitStart;\r
- UINT8 ValidBitLength;\r
- UINT64 Value;\r
+ REGISTER_TYPE RegisterType; // offset 0 - 3\r
+ UINT32 Index; // offset 4 - 7\r
+ UINT8 ValidBitStart; // offset 8\r
+ UINT8 ValidBitLength; // offset 9\r
+ UINT16 Reserved; // offset 10 - 11\r
+ UINT32 HighIndex; // offset 12-15, only valid for MemoryMapped\r
+ UINT64 Value; // offset 16-23\r
} CPU_REGISTER_TABLE_ENTRY;\r
\r
//\r
//\r
UINT32 InitialApicId;\r
//\r
- // Buffer of CPU_REGISTER_TABLE_ENTRY structures. This buffer must be\r
+ // Physical address of CPU_REGISTER_TABLE_ENTRY structures. This buffer must be\r
// allocated below 4GB from memory of type EfiACPIMemoryNVS.\r
//\r
- CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;\r
+ EFI_PHYSICAL_ADDRESS RegisterTableEntry;\r
} CPU_REGISTER_TABLE;\r
\r
//\r