UefiCpuPkg/SmmBaseHob.h: Add SMM Base HOB Data

[mirror_edk2.git] / UefiCpuPkg / Include / Guid / SmmBaseHob.h

diff --git a/UefiCpuPkg/Include/Guid/SmmBaseHob.h b/UefiCpuPkg/Include/Guid/SmmBaseHob.h
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+++ b/UefiCpuPkg/Include/Guid/SmmBaseHob.h
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+/** @file\r
+  The Smm Base HOB is used to store the information of:\r
+  * The relocated SmBase address in array for each processor.\r
+\r
+  The default Smbase for the x86 processor is 0x30000. When SMI happens, processor\r
+  runs the SMI handler at Smbase+0x8000. Also, the SMM save state area is within\r
+  Smbase+0x10000. Since it's the start address to store the processor save state\r
+  and code for the SMI entry point, those info are tiled within an SMRAM allocated\r
+  or reserved buffer. This tile size shall be enough to cover 3 parts:\r
+  1. Processor SMRAM Save State Map starts at Smbase + 0xfc00\r
+  2. Extra processor specific context start starts at Smbase + 0xfb00\r
+  3. SMI entry point starts at Smbase + 0x8000.\r
+  Besides, This size should be rounded up to nearest power of 2. The Smm Base HOB\r
+  producer should be responsible for reserving enough size.\r
+\r
+  One of the SMM initialization from processor perspective is to relocate and program\r
+  the new Smbase (in TSEG range) for each processor thread. When the Smbase relocation\r
+  happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB in HOB database\r
+  which tells the PiSmmCpuDxeSmm driver (which runs at a later phase) about the new\r
+  Smbase for each processor. PiSmmCpuDxeSmm driver installs the SMI handler at the\r
+  SMM_BASE_HOB.Smbase[Index]+0x8000 for processor index. When the HOB doesn't exist,\r
+  PiSmmCpuDxeSmm driver shall relocate and program the new Smbase itself.\r
+\r
+  Note:\r
+  1. Smbase relocation process needs to program the vender specific hardware\r
+  interface to set Smbase, it might be in the thread scope. It's doable to\r
+  program the hardware interface using DXE MP service protocol in PiSmmCpuDxeSmm\r
+  entry point. But, considering the standalone MM environment where the CpuMm\r
+  driver runs in a isolated environment and it cannot invoke any DXE or PEI MP\r
+  service, we recommend to put the hardware interface programming in a separate\r
+  PEI module instead of in the PiSmmCpuDxeSmm driver.\r
+\r
+  2. There is the hard requirement that SMI Entry Size <= 0x1000, data Size <=\r
+  0x1000 in PiSmmCpuDxeSmm. So, this require the allocated or reserved buffer in\r
+  SMRAM should be >= 0x2000.\r
+\r
+  Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef SMM_BASE_HOB_H_\r
+#define SMM_BASE_HOB_H_\r
+\r
+#define SMM_BASE_HOB_DATA_GUID \\r
+  { \\r
+    0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73}  \\r
+  }\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+  ///\r
+  /// ProcessorIndex tells which processor range this specific HOB instance described.\r
+  /// If ProcessorIndex is set to 0, it indicats the HOB describes the processor from\r
+  /// 0 to NumberOfProcessors - 1. The HOB list may contains multiple this HOB\r
+  /// instances. Each HOB instances describe the information for processor from\r
+  /// ProcessorIndex to ProcessorIndex + NumberOfProcessors - 1. The instance order in\r
+  /// the HOB list is random so consumer can not assume the ProcessorIndex of first\r
+  /// instance is 0.\r
+  ///\r
+  UINT32    ProcessorIndex;\r
+  ///\r
+  /// Describes the Number of all max supported processors.\r
+  ///\r
+  UINT32    NumberOfProcessors;\r
+  ///\r
+  /// Pointer to SmBase address for each processor.\r
+  ///\r
+  UINT64    SmBase[];\r
+} SMM_BASE_HOB_DATA;\r
+#pragma pack()\r
+\r
+extern EFI_GUID  gSmmBaseHobGuid;\r
+\r
+#endif\r