returned is a single 32-bit or 64-bit value, then a data structure is not\r
provided for that MSR.\r
\r
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
@par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1.\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Appendix A VMX Capability Reporting Facility, Section A.1.\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Appendix A VMX Capability Reporting Facility, Section A.6.\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
#define __ARCHITECTURAL_MSR_H__\r
\r
/**\r
- See Section 35.20, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r
+ See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r
\r
@param ECX MSR_IA32_P5_MC_ADDR (0x00000000)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- See Section 35.20, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r
+ See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r
\r
@param ECX MSR_IA32_P5_MC_TYPE (0x00000001)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- See Section 17.14, "Time-Stamp Counter.". Introduced at Display Family /\r
+ See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /\r
Display Model 05_01H.\r
\r
@param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)\r
/// 6] is set. If CPUID.01H:ECX[6] = 1.\r
///\r
UINT32 SenterGlobalEnable:1;\r
- UINT32 Reserved2:2;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to\r
+ /// enable runtime reconfiguration of SGX Launch Control via\r
+ /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.\r
+ ///\r
+ UINT32 SgxLaunchControlEnable:1;\r
///\r
/// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX\r
- /// leaf functions. This bit is supported only if CPUID.1:ECX.[bit 6] is\r
- /// set. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r
+ /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r
///\r
UINT32 SgxEnable:1;\r
UINT32 Reserved3:1;\r
} MSR_IA32_BIOS_SIGN_ID_REGISTER;\r
\r
\r
+/**\r
+ IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the\r
+ SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the\r
+ default value is the digest of Intel's signing key. Read permitted If\r
+ CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):\r
+ EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.\r
+\r
+ @param ECX MSR_IA32_SGXLEPUBKEYHASHn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);\r
+ AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);\r
+ @endcode\r
+ @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.\r
+ MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.\r
+ MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.\r
+ MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C\r
+#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D\r
+#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E\r
+#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F\r
+/// @}\r
+\r
+\r
/**\r
SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =\r
1.\r
UINT32 Valid:1;\r
UINT32 Reserved1:1;\r
///\r
- /// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the\r
- /// default treatment of SMIs and SMM. Executions of VMXOFF unblock SMIs\r
- /// unless bit 2 is 1 (the value of bit 0 is irrelevant).\r
+ /// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If\r
+ /// IA32_VMX_MISC[28].\r
///\r
UINT32 BlockSmi:1;\r
UINT32 Reserved2:9;\r
field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
**/\r
typedef struct {\r
+ ///\r
+ /// Different processors may use different MSEG revision identifiers. These\r
+ /// identifiers enable software to avoid using an MSEG header formatted for\r
+ /// one processor on a processor that uses a different format. Software can\r
+ /// discover the MSEG revision identifier that a processor uses by reading\r
+ /// the VMX capability MSR IA32_VMX_MISC.\r
+ //\r
UINT32 MsegHeaderRevision;\r
+ ///\r
+ /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field\r
+ /// is the IA-32e mode SMM feature bit. It indicates whether the logical\r
+ /// processor will be in IA-32e mode after the STM is activated.\r
+ ///\r
UINT32 MonitorFeatures;\r
UINT32 GdtrLimit;\r
UINT32 GdtrBaseOffset;\r
UINT32 EipOffset;\r
UINT32 EspOffset;\r
UINT32 Cr3Offset;\r
- //\r
- // Pad header so total size is 2KB\r
- //\r
+ ///\r
+ /// Pad header so total size is 2KB\r
+ ///\r
UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];\r
} MSEG_HEADER;\r
\r
+///\r
+/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER\r
+///\r
+#define STM_FEATURES_IA32E 0x1\r
+///\r
+/// @}\r
+///\r
\r
/**\r
Base address of the logical processor's SMRAM image (RO, SMM only). If\r
\r
/**\r
Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled\r
- Clock Modulation.". Introduced at Display Family / Display Model 0F_0H.\r
+ Clock Modulation.". If CPUID.01H:EDX[22] = 1.\r
\r
@param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)\r
@param EAX Lower 32-bits of MSR value.\r
UINT32 ExtendedOnDemandClockModulationDutyCycle:1;\r
///\r
/// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded\r
- /// values for target duty cycle modulation.\r
+ /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 OnDemandClockModulationDutyCycle:3;\r
///\r
/// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.\r
+ /// If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 OnDemandClockModulationEnable:1;\r
UINT32 Reserved1:27;\r
Thermal Interrupt Control (R/W) Enables and disables the generation of an\r
interrupt on temperature transitions detected with the processor's thermal\r
sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".\r
- Introduced at Display Family / Display Model 0F_0H.\r
+ If CPUID.01H:EDX[22] = 1\r
\r
@param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)\r
@param EAX Lower 32-bits of MSR value.\r
///\r
struct {\r
///\r
- /// [Bit 0] High-Temperature Interrupt Enable.\r
+ /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 HighTempEnable:1;\r
///\r
- /// [Bit 1] Low-Temperature Interrupt Enable.\r
+ /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 LowTempEnable:1;\r
///\r
- /// [Bit 2] PROCHOT# Interrupt Enable.\r
+ /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 PROCHOT_Enable:1;\r
///\r
- /// [Bit 3] FORCEPR# Interrupt Enable.\r
+ /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 FORCEPR_Enable:1;\r
///\r
/// [Bit 4] Critical Temperature Interrupt Enable.\r
+ /// If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 CriticalTempEnable:1;\r
UINT32 Reserved1:3;\r
///\r
- /// [Bits 14:8] Threshold #1 Value.\r
+ /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 Threshold1:7;\r
///\r
- /// [Bit 15] Threshold #1 Interrupt Enable.\r
+ /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 Threshold1Enable:1;\r
///\r
- /// [Bits 22:16] Threshold #2 Value.\r
+ /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 Threshold2:7;\r
///\r
- /// [Bit 23] Threshold #2 Interrupt Enable.\r
+ /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 Threshold2Enable:1;\r
///\r
/**\r
Thermal Status Information (RO) Contains status information about the\r
processor's thermal sensor and automatic thermal monitoring facilities. See\r
- Section 14.7.2, "Thermal Monitor". Introduced at Display Family / Display\r
- Model 0F_0H.\r
+ Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.\r
\r
@param ECX MSR_IA32_THERM_STATUS (0x0000019C)\r
@param EAX Lower 32-bits of MSR value.\r
///\r
struct {\r
///\r
- /// [Bit 0] Thermal Status (RO):.\r
+ /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 ThermalStatus:1;\r
///\r
- /// [Bit 1] Thermal Status Log (R/W):.\r
+ /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 ThermalStatusLog:1;\r
///\r
- /// [Bit 2] PROCHOT # or FORCEPR# event (RO).\r
+ /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 PROCHOT_FORCEPR_Event:1;\r
///\r
- /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0).\r
+ /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 PROCHOT_FORCEPR_Log:1;\r
///\r
- /// [Bit 4] Critical Temperature Status (RO).\r
+ /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 CriticalTempStatus:1;\r
///\r
/// [Bit 5] Critical Temperature Status log (R/WC0).\r
+ /// If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 CriticalTempStatusLog:1;\r
///\r
/// automatically reduce power consumption in response to TCC activation.\r
/// 0 = Disabled. Note: In some products clearing this bit might be\r
/// ignored in critical thermal conditions, and TM1, TM2 and adaptive\r
- /// thermal throttling will still be activated. Introduced at Display\r
- /// Family / Display Model 0F_0H.\r
+ /// thermal throttling will still be activated. The default value of this\r
+ /// field varies with product. See respective tables where default value is\r
+ /// listed. Introduced at Display Family / Display Model 0F_0H.\r
///\r
UINT32 AutomaticThermalControlCircuit:1;\r
UINT32 Reserved2:3;\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] Precise Event Based Sampling (PEBS) Unavailable (RO) 1 =\r
+ /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =\r
/// PEBS is not supported; 0 = PEBS is supported. Introduced at Display\r
/// Family / Display Model 06_0FH.\r
///\r
UINT32 Reserved6:3;\r
///\r
/// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H\r
- /// returns a maximum value in EAX[7:0] of 3. BIOS should contain a setup\r
+ /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup\r
/// question that allows users to specify when the installed OS does not\r
- /// support CPUID functions greater than 3. Before setting this bit, BIOS\r
+ /// support CPUID functions greater than 2. Before setting this bit, BIOS\r
/// must execute the CPUID.0H and examine the maximum value returned in\r
- /// EAX[7:0]. If the maximum value is greater than 3, the bit is\r
- /// supported. Otherwise, the bit is not supported. Writing to this bit\r
- /// when the maximum value is greater than 3 may generate a #GP exception.\r
+ /// EAX[7:0]. If the maximum value is greater than 2, this bit is\r
+ /// supported. Otherwise, this bit is not supported. Setting this bit when\r
+ /// the maximum value is not greater than 2 may generate a #GP exception.\r
/// Setting this bit may cause unexpected behavior in software that\r
- /// depends on the availability of CPUID leaves greater than 3. Introduced\r
+ /// depends on the availability of CPUID leaves greater than 2. Introduced\r
/// at Display Family / Display Model 0F_03H.\r
///\r
UINT32 LimitCpuidMaxval:1;\r
\r
\r
/**\r
- SMRR Range Mask. (Writeable only in SMM) Range Mask of SMM memory range. If\r
+ SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If\r
IA32_MTRRCAP[SMRR] = 1.\r
\r
@param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)\r
\r
\r
/**\r
- Fixed-Function Performance Counter 1 0 (R/W): Counts CPU_CLK_Unhalted.Core.\r
- If CPUID.0AH: EDX[4:0] > 1.\r
+ Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If\r
+ CPUID.0AH: EDX[4:0] > 1.\r
\r
@param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Fixed-Function Performance Counter 0 0 (R/W): Counts CPU_CLK_Unhalted.Ref.\r
- If CPUID.0AH: EDX[4:0] > 2.\r
+ Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If\r
+ CPUID.0AH: EDX[4:0] > 2.\r
\r
@param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)\r
@param EAX Lower 32-bits of MSR value.\r
///\r
UINT32 MemoryType:4;\r
///\r
- /// [Bit 54] If bit 54 is read as 1, the logical processor reports\r
- /// information in the VM-exit instruction-information field on VM exits\r
- /// due to execution of the INS and OUTS instructions. This reporting is\r
- /// done only if this bit is read as 1.\r
+ /// [Bit 54] If bit 54 is read as 1, the processor reports information in\r
+ /// the VM-exit instruction-information field on VM exitsdue to execution\r
+ /// of the INS and OUTS instructions (see Section 27.2.4). This reporting\r
+ /// is done only if this bit is read as 1.\r
///\r
UINT32 InsOutsReporting:1;\r
///\r
/// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).\r
///\r
UINT32 WaitForSipiActivityStateSupported:1;\r
- UINT32 Reserved1:6;\r
+ UINT32 Reserved1:5;\r
+ ///\r
+ /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used\r
+ /// in VMX operation. If the processor supports Intel PT but does not allow\r
+ /// it to be used in VMX operation, execution of VMXON clears\r
+ /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30);\r
+ /// any attempt to set that bit while in VMX operation (including VMX root\r
+ /// operation) using the WRMSR instruction causes a general-protection\r
+ /// exception.\r
+ ///\r
+ UINT32 ProcessorTraceSupported:1;\r
///\r
/// [Bit 15] If read as 1, the RDMSR instruction can be used in system-\r
/// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).\r
- /// See Section 34.15.6.4.\r
+ /// See Section 34.15.6.3.\r
///\r
UINT32 SmBaseMsrSupported:1;\r
///\r
/// information fields.\r
///\r
UINT32 VmWriteSupported:1;\r
- UINT32 Reserved2:2;\r
+ ///\r
+ /// [Bit 30] If read as 1, VM entry allows injection of a software\r
+ /// interrupt, software exception, or privileged software exception with an\r
+ /// instruction length of 0.\r
+ ///\r
+ UINT32 VmInjectSupported:1;\r
+ UINT32 Reserved2:1;\r
///\r
/// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the\r
/// processor.\r
///\r
struct {\r
///\r
- /// [Bit 0] Lock. See Section 42.12.3, "Interactions with Authenticated\r
+ /// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated\r
/// Code Modules (ACMs)".\r
///\r
UINT32 Lock:1;\r
UINT32 Reserved1:15;\r
///\r
- /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.12.3, "Interactions with\r
+ /// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with\r
/// Authenticated Code Modules (ACMs)".\r
///\r
UINT32 SGX_SVN_SINIT:8;\r
UINT64 Uint64;\r
} MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;\r
\r
+/**\r
+ Format of ToPA table entries.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+ ///\r
+ UINT32 END:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+ ///\r
+ UINT32 INT:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+ ///\r
+ UINT32 STOP:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 6:9] Indicates the size of the associated output region. See Section\r
+ /// 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+ ///\r
+ UINT32 Size:4;\r
+ UINT32 Reserved4:2;\r
+ ///\r
+ /// [Bit 12:31] Output Region Base Physical Address low part.\r
+ /// [Bit 12:31] Output Region Base Physical Address [12:63] value to match.\r
+ /// ATTENTION: The size of the address field is determined by the processor's\r
+ /// physical-address width (MAXPHYADDR) in bits, as reported in\r
+ /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.\r
+ /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.\r
+ /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+ ///\r
+ UINT32 Base:20;\r
+ ///\r
+ /// [Bit 32:63] Output Region Base Physical Address high part.\r
+ /// [Bit 32:63] Output Region Base Physical Address [12:63] value to match.\r
+ /// ATTENTION: The size of the address field is determined by the processor's\r
+ /// physical-address width (MAXPHYADDR) in bits, as reported in\r
+ /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.\r
+ /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.\r
+ /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+ ///\r
+ UINT32 BaseHi:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} RTIT_TOPA_TABLE_ENTRY;\r
+\r
+///\r
+/// The size of the associated output region usd by Topa.\r
+///\r
+typedef enum {\r
+ RtitTopaMemorySize4K = 0,\r
+ RtitTopaMemorySize8K,\r
+ RtitTopaMemorySize16K,\r
+ RtitTopaMemorySize32K,\r
+ RtitTopaMemorySize64K,\r
+ RtitTopaMemorySize128K,\r
+ RtitTopaMemorySize256K,\r
+ RtitTopaMemorySize512K,\r
+ RtitTopaMemorySize1M,\r
+ RtitTopaMemorySize2M,\r
+ RtitTopaMemorySize4M,\r
+ RtitTopaMemorySize8M,\r
+ RtitTopaMemorySize16M,\r
+ RtitTopaMemorySize32M,\r
+ RtitTopaMemorySize64M,\r
+ RtitTopaMemorySize128M\r
+} RTIT_TOPA_MEMORY_SIZE;\r
\r
/**\r
Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r
/// [Bit 3] User.\r
///\r
UINT32 User:1;\r
- UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 4] PwrEvtEn.\r
+ ///\r
+ UINT32 PwrEvtEn:1;\r
+ ///\r
+ /// [Bit 5] FUPonPTW.\r
+ ///\r
+ UINT32 FUPonPTW:1;\r
///\r
/// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).\r
///\r
/// [Bit 11] DisRETC.\r
///\r
UINT32 DisRETC:1;\r
- UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 12] PTWEn.\r
+ ///\r
+ UINT32 PTWEn:1;\r
///\r
/// [Bit 13] BranchEn.\r
///\r
\r
\r
/**\r
- DS Save Area (R/W) Points to the linear address of the first byte of the DS\r
+ DS Save Area (R/W) Points to the linear address of the first byte of the DS\r
buffer management area, which is used to manage the BTS and PEBS buffers.\r
- See Section 18.12.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]\r
- = 1.\r
-\r
- [Bits 31..0] The linear address of the first byte of the DS buffer\r
- management area, if not in IA-32e mode.\r
-\r
- [Bits 63..0] The linear address of the first byte of the DS buffer\r
- management area, if IA-32e mode is active.\r
+ See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If(\r
+ CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS\r
+ buffer management area, if IA-32e mode is active.\r
\r
@param ECX MSR_IA32_DS_AREA (0x00000600)\r
@param EAX Lower 32-bits of MSR value.\r
UINT64 Uint64;\r
} MSR_IA32_L3_QOS_CFG_REGISTER;\r
\r
+/**\r
+ L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ).\r
+\r
+ @param ECX MSR_IA32_L2_QOS_CFG (0x00000C82)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_L2_QOS_CFG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG);\r
+ AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.\r
+**/\r
+#define MSR_IA32_L2_QOS_CFG 0x00000C82\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate\r
+ /// in Code and Data Prioritization (CDP) mode.\r
+ ///\r
+ UINT32 Enable:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_L2_QOS_CFG_REGISTER;\r
\r
/**\r
Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]\r
\r
\r
/**\r
- Resource Association Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] =\r
- 1 ).\r
+ Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]\r
+ =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).\r
\r
@param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)\r
@param EAX Lower 32-bits of MSR value.\r
**/\r
#define MSR_IA32_LSTAR 0xC0000082\r
\r
+/**\r
+ IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL\r
+ instruction is not recognized in compatibility mode. If\r
+ CPUID.80000001:EDX.[29] = 1.\r
+\r
+ @param ECX MSR_IA32_CSTAR (0xC0000083)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_CSTAR);\r
+ AsmWriteMsr64 (MSR_IA32_CSTAR, Msr);\r
+ @endcode\r
+ @note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.\r
+**/\r
+#define MSR_IA32_CSTAR 0xC0000083\r
\r
/**\r
System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.\r
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