field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
**/\r
typedef struct {\r
+ ///\r
+ /// Different processors may use different MSEG revision identifiers. These\r
+ /// identifiers enable software to avoid using an MSEG header formatted for\r
+ /// one processor on a processor that uses a different format. Software can\r
+ /// discover the MSEG revision identifier that a processor uses by reading\r
+ /// the VMX capability MSR IA32_VMX_MISC.\r
+ //\r
UINT32 MsegHeaderRevision;\r
+ ///\r
+ /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field\r
+ /// is the IA-32e mode SMM feature bit. It indicates whether the logical\r
+ /// processor will be in IA-32e mode after the STM is activated.\r
+ ///\r
UINT32 MonitorFeatures;\r
UINT32 GdtrLimit;\r
UINT32 GdtrBaseOffset;\r
UINT32 EipOffset;\r
UINT32 EspOffset;\r
UINT32 Cr3Offset;\r
- //\r
- // Pad header so total size is 2KB\r
- //\r
+ ///\r
+ /// Pad header so total size is 2KB\r
+ ///\r
UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];\r
} MSEG_HEADER;\r
\r
+///\r
+/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER\r
+///\r
+#define STM_FEATURES_IA32E 0x1\r
+///\r
+/// @}\r
+///\r
\r
/**\r
Base address of the logical processor's SMRAM image (RO, SMM only). If\r
/// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used\r
/// in VMX operation. If the processor supports Intel PT but does not allow\r
/// it to be used in VMX operation, execution of VMXON clears\r
- /// IA32_RTIT_CTL.TraceEn (see \93VMXON\97Enter VMX Operation\94 in Chapter 30);\r
+ /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30);\r
/// any attempt to set that bit while in VMX operation (including VMX root\r
/// operation) using the WRMSR instruction causes a general-protection\r
/// exception.\r