\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.1.\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+ September 2016, Appendix A VMX Capability Reporting Facility, Section A.1.\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+ September 2016, Appendix A VMX Capability Reporting Facility, Section A.6.\r
\r
**/\r
\r
#define __ARCHITECTURAL_MSR_H__\r
\r
/**\r
- See Section 35.20, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r
+ See Section 35.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r
\r
@param ECX MSR_IA32_P5_MC_ADDR (0x00000000)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- See Section 35.20, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r
+ See Section 35.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r
\r
@param ECX MSR_IA32_P5_MC_TYPE (0x00000001)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- See Section 17.14, "Time-Stamp Counter.". Introduced at Display Family /\r
+ See Section 17.15, "Time-Stamp Counter.". Introduced at Display Family /\r
Display Model 05_01H.\r
\r
@param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)\r
/// 6] is set. If CPUID.01H:ECX[6] = 1.\r
///\r
UINT32 SenterGlobalEnable:1;\r
- UINT32 Reserved2:2;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to\r
+ /// enable runtime reconfiguration of SGX Launch Control via\r
+ /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.\r
+ ///\r
+ UINT32 SgxLaunchControlEnable:1;\r
///\r
/// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX\r
- /// leaf functions. This bit is supported only if CPUID.1:ECX.[bit 6] is\r
- /// set. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r
+ /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r
///\r
UINT32 SgxEnable:1;\r
UINT32 Reserved3:1;\r
\r
\r
/**\r
- SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1. CPUID.01H: ECX[6] =\r
+ IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the\r
+ SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the\r
+ default value is the digest of Intel's signing key. Read permitted If\r
+ CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):\r
+ EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.\r
+\r
+ @param ECX MSR_IA32_SGXLEPUBKEYHASHn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);\r
+ AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);\r
+ @endcode\r
+ @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.\r
+ MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.\r
+ MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.\r
+ MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C\r
+#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D\r
+#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E\r
+#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F\r
+/// @}\r
+\r
+\r
+/**\r
+ SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =\r
1.\r
\r
@param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)\r
UINT64 Uint64;\r
} MSR_IA32_SMM_MONITOR_CTL_REGISTER;\r
\r
+/**\r
+ MSEG header that is located at the physical address specified by the MsegBase\r
+ field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
+**/\r
+typedef struct {\r
+ ///\r
+ /// Different processors may use different MSEG revision identifiers. These\r
+ /// identifiers enable software to avoid using an MSEG header formatted for\r
+ /// one processor on a processor that uses a different format. Software can\r
+ /// discover the MSEG revision identifier that a processor uses by reading\r
+ /// the VMX capability MSR IA32_VMX_MISC.\r
+ //\r
+ UINT32 MsegHeaderRevision;\r
+ ///\r
+ /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field\r
+ /// is the IA-32e mode SMM feature bit. It indicates whether the logical\r
+ /// processor will be in IA-32e mode after the STM is activated.\r
+ ///\r
+ UINT32 MonitorFeatures;\r
+ UINT32 GdtrLimit;\r
+ UINT32 GdtrBaseOffset;\r
+ UINT32 CsSelector;\r
+ UINT32 EipOffset;\r
+ UINT32 EspOffset;\r
+ UINT32 Cr3Offset;\r
+ ///\r
+ /// Pad header so total size is 2KB\r
+ ///\r
+ UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];\r
+} MSEG_HEADER;\r
+\r
+///\r
+/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER\r
+///\r
+#define STM_FEATURES_IA32E 0x1\r
+///\r
+/// @}\r
+///\r
\r
/**\r
Base address of the logical processor's SMRAM image (RO, SMM only). If\r
\r
/**\r
Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled\r
- Clock Modulation.". Introduced at Display Family / Display Model 0F_0H.\r
+ Clock Modulation.". If CPUID.01H:EDX[22] = 1.\r
\r
@param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)\r
@param EAX Lower 32-bits of MSR value.\r
UINT32 ExtendedOnDemandClockModulationDutyCycle:1;\r
///\r
/// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded\r
- /// values for target duty cycle modulation.\r
+ /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 OnDemandClockModulationDutyCycle:3;\r
///\r
/// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.\r
+ /// If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 OnDemandClockModulationEnable:1;\r
UINT32 Reserved1:27;\r
Thermal Interrupt Control (R/W) Enables and disables the generation of an\r
interrupt on temperature transitions detected with the processor's thermal\r
sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".\r
- Introduced at Display Family / Display Model 0F_0H.\r
+ If CPUID.01H:EDX[22] = 1\r
\r
@param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)\r
@param EAX Lower 32-bits of MSR value.\r
///\r
struct {\r
///\r
- /// [Bit 0] High-Temperature Interrupt Enable.\r
+ /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 HighTempEnable:1;\r
///\r
- /// [Bit 1] Low-Temperature Interrupt Enable.\r
+ /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 LowTempEnable:1;\r
///\r
- /// [Bit 2] PROCHOT# Interrupt Enable.\r
+ /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 PROCHOT_Enable:1;\r
///\r
- /// [Bit 3] FORCEPR# Interrupt Enable.\r
+ /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 FORCEPR_Enable:1;\r
///\r
/// [Bit 4] Critical Temperature Interrupt Enable.\r
+ /// If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 CriticalTempEnable:1;\r
UINT32 Reserved1:3;\r
///\r
- /// [Bits 14:8] Threshold #1 Value.\r
+ /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 Threshold1:7;\r
///\r
- /// [Bit 15] Threshold #1 Interrupt Enable.\r
+ /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 Threshold1Enable:1;\r
///\r
- /// [Bits 22:16] Threshold #2 Value.\r
+ /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 Threshold2:7;\r
///\r
- /// [Bit 23] Threshold #2 Interrupt Enable.\r
+ /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 Threshold2Enable:1;\r
///\r
/**\r
Thermal Status Information (RO) Contains status information about the\r
processor's thermal sensor and automatic thermal monitoring facilities. See\r
- Section 14.7.2, "Thermal Monitor". Introduced at Display Family / Display\r
- Model 0F_0H.\r
+ Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.\r
\r
@param ECX MSR_IA32_THERM_STATUS (0x0000019C)\r
@param EAX Lower 32-bits of MSR value.\r
///\r
struct {\r
///\r
- /// [Bit 0] Thermal Status (RO):.\r
+ /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 ThermalStatus:1;\r
///\r
- /// [Bit 1] Thermal Status Log (R/W):.\r
+ /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 ThermalStatusLog:1;\r
///\r
- /// [Bit 2] PROCHOT # or FORCEPR# event (RO).\r
+ /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 PROCHOT_FORCEPR_Event:1;\r
///\r
- /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0).\r
+ /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 PROCHOT_FORCEPR_Log:1;\r
///\r
- /// [Bit 4] Critical Temperature Status (RO).\r
+ /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 CriticalTempStatus:1;\r
///\r
/// [Bit 5] Critical Temperature Status log (R/WC0).\r
+ /// If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 CriticalTempStatusLog:1;\r
///\r
/// automatically reduce power consumption in response to TCC activation.\r
/// 0 = Disabled. Note: In some products clearing this bit might be\r
/// ignored in critical thermal conditions, and TM1, TM2 and adaptive\r
- /// thermal throttling will still be activated. Introduced at Display\r
- /// Family / Display Model 0F_0H.\r
+ /// thermal throttling will still be activated. The default value of this\r
+ /// field varies with product. See respective tables where default value is\r
+ /// listed. Introduced at Display Family / Display Model 0F_0H.\r
///\r
UINT32 AutomaticThermalControlCircuit:1;\r
UINT32 Reserved2:3;\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] Precise Event Based Sampling (PEBS) Unavailable (RO) 1 =\r
+ /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =\r
/// PEBS is not supported; 0 = PEBS is supported. Introduced at Display\r
/// Family / Display Model 06_0FH.\r
///\r
UINT32 Reserved6:3;\r
///\r
/// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H\r
- /// returns a maximum value in EAX[7:0] of 3. BIOS should contain a setup\r
+ /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup\r
/// question that allows users to specify when the installed OS does not\r
- /// support CPUID functions greater than 3. Before setting this bit, BIOS\r
+ /// support CPUID functions greater than 2. Before setting this bit, BIOS\r
/// must execute the CPUID.0H and examine the maximum value returned in\r
- /// EAX[7:0]. If the maximum value is greater than 3, the bit is\r
- /// supported. Otherwise, the bit is not supported. Writing to this bit\r
- /// when the maximum value is greater than 3 may generate a #GP exception.\r
+ /// EAX[7:0]. If the maximum value is greater than 2, this bit is\r
+ /// supported. Otherwise, this bit is not supported. Setting this bit when\r
+ /// the maximum value is not greater than 2 may generate a #GP exception.\r
/// Setting this bit may cause unexpected behavior in software that\r
- /// depends on the availability of CPUID leaves greater than 3. Introduced\r
+ /// depends on the availability of CPUID leaves greater than 2. Introduced\r
/// at Display Family / Display Model 0F_03H.\r
///\r
UINT32 LimitCpuidMaxval:1;\r
\r
\r
/**\r
- Fixed-Function Performance Counter 1 0 (R/W): Counts CPU_CLK_Unhalted.Core.\r
- If CPUID.0AH: EDX[4:0] > 1.\r
+ Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If\r
+ CPUID.0AH: EDX[4:0] > 1.\r
\r
@param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Fixed-Function Performance Counter 0 0 (R/W): Counts CPU_CLK_Unhalted.Ref.\r
- If CPUID.0AH: EDX[4:0] > 2.\r
+ Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If\r
+ CPUID.0AH: EDX[4:0] > 2.\r
\r
@param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)\r
@param EAX Lower 32-bits of MSR value.\r
\r
<b>Example usage</b>\r
@code\r
- UINT64 Msr;\r
+ MSR_IA32_VMX_BASIC_REGISTER Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_BASIC);\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);\r
@endcode\r
@note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.\r
**/\r
#define MSR_IA32_VMX_BASIC 0x00000480\r
\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_VMX_BASIC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 30:0] VMCS revision identifier used by the processor. Processors\r
+ /// that use the same VMCS revision identifier use the same size for VMCS\r
+ /// regions (see subsequent item on bits 44:32).\r
+ ///\r
+ /// @note Earlier versions of this manual specified that the VMCS revision\r
+ /// identifier was a 32-bit field in bits 31:0 of this MSR. For all\r
+ /// processors produced prior to this change, bit 31 of this MSR was read\r
+ /// as 0.\r
+ ///\r
+ UINT32 VmcsRevisonId:31;\r
+ UINT32 MustBeZero:1;\r
+ ///\r
+ /// [Bit 44:32] Reports the number of bytes that software should allocate\r
+ /// for the VMXON region and any VMCS region. It is a value greater than\r
+ /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).\r
+ ///\r
+ UINT32 VmcsSize:13;\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bit 48] Indicates the width of the physical addresses that may be used\r
+ /// for the VMXON region, each VMCS, and data structures referenced by\r
+ /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX\r
+ /// transitions). If the bit is 0, these addresses are limited to the\r
+ /// processor's physical-address width. If the bit is 1, these addresses\r
+ /// are limited to 32 bits. This bit is always 0 for processors that\r
+ /// support Intel 64 architecture.\r
+ ///\r
+ /// @note On processors that support Intel 64 architecture, the pointer\r
+ /// must not set bits beyond the processor's physical address width.\r
+ ///\r
+ UINT32 VmcsAddressWidth:1;\r
+ ///\r
+ /// [Bit 49] If bit 49 is read as 1, the logical processor supports the\r
+ /// dual-monitor treatment of system-management interrupts and\r
+ /// system-management mode. See Section 34.15 for details of this treatment.\r
+ ///\r
+ UINT32 DualMonitor:1;\r
+ ///\r
+ /// [Bit 53:50] report the memory type that should be used for the VMCS,\r
+ /// for data structures referenced by pointers in the VMCS (I/O bitmaps,\r
+ /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG\r
+ /// header. If software needs to access these data structures (e.g., to\r
+ /// modify the contents of the MSR bitmaps), it can configure the paging\r
+ /// structures to map them into the linear-address space. If it does so,\r
+ /// it should establish mappings that use the memory type reported bits\r
+ /// 53:50 in this MSR.\r
+ ///\r
+ /// As of this writing, all processors that support VMX operation indicate\r
+ /// the write-back type.\r
+ ///\r
+ /// If software needs to access these data structures (e.g., to modify\r
+ /// the contents of the MSR bitmaps), it can configure the paging\r
+ /// structures to map them into the linear-address space. If it does so,\r
+ /// it should establish mappings that use the memory type reported in this\r
+ /// MSR.\r
+ ///\r
+ /// @note Alternatively, software may map any of these regions or\r
+ /// structures with the UC memory type. (This may be necessary for the MSEG\r
+ /// header.) Doing so is discouraged unless necessary as it will cause the\r
+ /// performance of software accesses to those structures to suffer.\r
+ ///\r
+ ///\r
+ UINT32 MemoryType:4;\r
+ ///\r
+ /// [Bit 54] If bit 54 is read as 1, the processor reports information in\r
+ /// the VM-exit instruction-information field on VM exitsdue to execution\r
+ /// of the INS and OUTS instructions (see Section 27.2.4). This reporting\r
+ /// is done only if this bit is read as 1.\r
+ ///\r
+ UINT32 InsOutsReporting:1;\r
+ ///\r
+ /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may\r
+ /// be cleared to 0. See Appendix A.2 for details. It also reports support\r
+ /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,\r
+ /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and\r
+ /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,\r
+ /// Appendix A.4, and Appendix A.5 for details.\r
+ ///\r
+ UINT32 VmxControls:1;\r
+ UINT32 Reserved2:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_VMX_BASIC_REGISTER;\r
+\r
+///\r
+/// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType\r
+///\r
+#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00\r
+#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06\r
+///\r
+/// @}\r
+///\r
+\r
\r
/**\r
Capability Reporting Register of Pinbased VM-execution Controls (R/O) See\r
\r
<b>Example usage</b>\r
@code\r
- UINT64 Msr;\r
+ IA32_VMX_MISC_REGISTER Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_MISC);\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);\r
@endcode\r
@note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.\r
**/\r
#define MSR_IA32_VMX_MISC 0x00000485\r
\r
+/**\r
+ MSR information returned for MSR index #IA32_VMX_MISC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] Reports a value X that specifies the relationship between the\r
+ /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).\r
+ /// Specifically, the VMX-preemption timer (if it is active) counts down by\r
+ /// 1 every time bit X in the TSC changes due to a TSC increment.\r
+ ///\r
+ UINT32 VmxTimerRatio:5;\r
+ ///\r
+ /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA\r
+ /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more\r
+ /// details. This bit is read as 1 on any logical processor that supports\r
+ /// the 1-setting of the "unrestricted guest" VM-execution control.\r
+ ///\r
+ UINT32 VmExitEferLma:1;\r
+ ///\r
+ /// [Bit 6] reports (if set) the support for activity state 1 (HLT).\r
+ ///\r
+ UINT32 HltActivityStateSupported:1;\r
+ ///\r
+ /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).\r
+ ///\r
+ UINT32 ShutdownActivityStateSupported:1;\r
+ ///\r
+ /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).\r
+ ///\r
+ UINT32 WaitForSipiActivityStateSupported:1;\r
+ UINT32 Reserved1:5;\r
+ ///\r
+ /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used\r
+ /// in VMX operation. If the processor supports Intel PT but does not allow\r
+ /// it to be used in VMX operation, execution of VMXON clears\r
+ /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30);\r
+ /// any attempt to set that bit while in VMX operation (including VMX root\r
+ /// operation) using the WRMSR instruction causes a general-protection\r
+ /// exception.\r
+ ///\r
+ UINT32 ProcessorTraceSupported:1;\r
+ ///\r
+ /// [Bit 15] If read as 1, the RDMSR instruction can be used in system-\r
+ /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).\r
+ /// See Section 34.15.6.3.\r
+ ///\r
+ UINT32 SmBaseMsrSupported:1;\r
+ ///\r
+ /// [Bits 24:16] Indicate the number of CR3-target values supported by the\r
+ /// processor. This number is a value between 0 and 256, inclusive (bit 24\r
+ /// is set if and only if bits 23:16 are clear).\r
+ ///\r
+ UINT32 NumberOfCr3TargetValues:9;\r
+ ///\r
+ /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum\r
+ /// number of MSRs that should appear in the VM-exit MSR-store list, the\r
+ /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if\r
+ /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the\r
+ /// recommended maximum number of MSRs to be included in each list. If the\r
+ /// limit is exceeded, undefined processor behavior may result (including a\r
+ /// machine check during the VMX transition).\r
+ ///\r
+ UINT32 MsrStoreListMaximum:3;\r
+ ///\r
+ /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set\r
+ /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1\r
+ /// (see Section 34.14.4).\r
+ ///\r
+ UINT32 BlockSmiSupported:1;\r
+ ///\r
+ /// [Bit 29] read as 1, software can use VMWRITE to write to any supported\r
+ /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit\r
+ /// information fields.\r
+ ///\r
+ UINT32 VmWriteSupported:1;\r
+ ///\r
+ /// [Bit 30] If read as 1, VM entry allows injection of a software\r
+ /// interrupt, software exception, or privileged software exception with an\r
+ /// instruction length of 0.\r
+ ///\r
+ UINT32 VmInjectSupported:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the\r
+ /// processor.\r
+ ///\r
+ UINT32 MsegRevisionIdentifier:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} IA32_VMX_MISC_REGISTER;\r
+\r
\r
/**\r
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,\r
///\r
struct {\r
///\r
- /// [Bit 0] Lock. See Section 42.12.3, "Interactions with Authenticated\r
+ /// [Bit 0] Lock. See Section 42.11.3, "Interactions with Authenticated\r
/// Code Modules (ACMs)".\r
///\r
UINT32 Lock:1;\r
UINT32 Reserved1:15;\r
///\r
- /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.12.3, "Interactions with\r
+ /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.11.3, "Interactions with\r
/// Authenticated Code Modules (ACMs)".\r
///\r
UINT32 SGX_SVN_SINIT:8;\r
/**\r
DS Save Area (R/W) Points to the linear address of the first byte of the DS\r
buffer management area, which is used to manage the BTS and PEBS buffers.\r
- See Section 18.12.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]\r
+ See Section 18.15.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]\r
= 1.\r
\r
[Bits 31..0] The linear address of the first byte of the DS buffer\r
\r
\r
/**\r
- Resource Association Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] =\r
- 1 ).\r
+ Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]\r
+ =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).\r
\r
@param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)\r
@param EAX Lower 32-bits of MSR value.\r
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