\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.1.\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+ September 2016, Appendix A VMX Capability Reporting Facility, Section A.1.\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+ September 2016, Appendix A VMX Capability Reporting Facility, Section A.6.\r
\r
**/\r
\r
#define __ARCHITECTURAL_MSR_H__\r
\r
/**\r
- See Section 35.20, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r
+ See Section 35.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r
\r
@param ECX MSR_IA32_P5_MC_ADDR (0x00000000)\r
@param EAX Lower 32-bits of MSR value.\r
Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);\r
AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);\r
@endcode\r
+ @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.\r
**/\r
#define MSR_IA32_P5_MC_ADDR 0x00000000\r
\r
\r
/**\r
- See Section 35.20, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r
+ See Section 35.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r
\r
@param ECX MSR_IA32_P5_MC_TYPE (0x00000001)\r
@param EAX Lower 32-bits of MSR value.\r
Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);\r
AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);\r
@endcode\r
+ @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.\r
**/\r
#define MSR_IA32_P5_MC_TYPE 0x00000001\r
\r
Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);\r
AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);\r
@endcode\r
+ @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.\r
**/\r
#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006\r
\r
\r
/**\r
- See Section 17.14, "Time-Stamp Counter.". Introduced at Display Family /\r
+ See Section 17.15, "Time-Stamp Counter.". Introduced at Display Family /\r
Display Model 05_01H.\r
\r
@param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)\r
Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);\r
AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);\r
@endcode\r
+ @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.\r
**/\r
#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);\r
@endcode\r
+ @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.\r
**/\r
#define MSR_IA32_PLATFORM_ID 0x00000017\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.\r
**/\r
#define MSR_IA32_APIC_BASE 0x0000001B\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);\r
AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r
**/\r
#define MSR_IA32_FEATURE_CONTROL 0x0000003A\r
\r
/// 6] is set. If CPUID.01H:ECX[6] = 1.\r
///\r
UINT32 SenterGlobalEnable:1;\r
- UINT32 Reserved2:2;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to\r
+ /// enable runtime reconfiguration of SGX Launch Control via\r
+ /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.\r
+ ///\r
+ UINT32 SgxLaunchControlEnable:1;\r
///\r
/// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX\r
- /// leaf functions. This bit is supported only if CPUID.1:ECX.[bit 6] is\r
- /// set. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r
+ /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r
///\r
UINT32 SgxEnable:1;\r
UINT32 Reserved3:1;\r
Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);\r
AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);\r
@endcode\r
+ @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.\r
**/\r
#define MSR_IA32_TSC_ADJUST 0x0000003B\r
\r
Msr = 0;\r
AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);\r
@endcode\r
+ @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.\r
**/\r
#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);\r
@endcode\r
+ @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.\r
**/\r
#define MSR_IA32_BIOS_SIGN_ID 0x0000008B\r
\r
\r
\r
/**\r
- SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1. CPUID.01H: ECX[6] =\r
+ IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the\r
+ SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the\r
+ default value is the digest of Intel's signing key. Read permitted If\r
+ CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):\r
+ EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.\r
+\r
+ @param ECX MSR_IA32_SGXLEPUBKEYHASHn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);\r
+ AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);\r
+ @endcode\r
+ @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.\r
+ MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.\r
+ MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.\r
+ MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C\r
+#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D\r
+#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E\r
+#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F\r
+/// @}\r
+\r
+\r
+/**\r
+ SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =\r
1.\r
\r
@param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);\r
AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.\r
**/\r
#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B\r
\r
UINT64 Uint64;\r
} MSR_IA32_SMM_MONITOR_CTL_REGISTER;\r
\r
+/**\r
+ MSEG header that is located at the physical address specified by the MsegBase\r
+ field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
+**/\r
+typedef struct {\r
+ ///\r
+ /// Different processors may use different MSEG revision identifiers. These\r
+ /// identifiers enable software to avoid using an MSEG header formatted for\r
+ /// one processor on a processor that uses a different format. Software can\r
+ /// discover the MSEG revision identifier that a processor uses by reading\r
+ /// the VMX capability MSR IA32_VMX_MISC.\r
+ //\r
+ UINT32 MsegHeaderRevision;\r
+ ///\r
+ /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field\r
+ /// is the IA-32e mode SMM feature bit. It indicates whether the logical\r
+ /// processor will be in IA-32e mode after the STM is activated.\r
+ ///\r
+ UINT32 MonitorFeatures;\r
+ UINT32 GdtrLimit;\r
+ UINT32 GdtrBaseOffset;\r
+ UINT32 CsSelector;\r
+ UINT32 EipOffset;\r
+ UINT32 EspOffset;\r
+ UINT32 Cr3Offset;\r
+ ///\r
+ /// Pad header so total size is 2KB\r
+ ///\r
+ UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];\r
+} MSEG_HEADER;\r
+\r
+///\r
+/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER\r
+///\r
+#define STM_FEATURES_IA32E 0x1\r
+///\r
+/// @}\r
+///\r
\r
/**\r
Base address of the logical processor's SMRAM image (RO, SMM only). If\r
\r
Msr = AsmReadMsr64 (MSR_IA32_SMBASE);\r
@endcode\r
+ @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.\r
**/\r
#define MSR_IA32_SMBASE 0x0000009E\r
\r
Msr = AsmReadMsr64 (MSR_IA32_PMC0);\r
AsmWriteMsr64 (MSR_IA32_PMC0, Msr);\r
@endcode\r
+ @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.\r
+ MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.\r
+ MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.\r
+ MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.\r
+ MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.\r
+ MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.\r
+ MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.\r
+ MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.\r
@{\r
**/\r
#define MSR_IA32_PMC0 0x000000C1\r
Msr = AsmReadMsr64 (MSR_IA32_MPERF);\r
AsmWriteMsr64 (MSR_IA32_MPERF, Msr);\r
@endcode\r
+ @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.\r
**/\r
#define MSR_IA32_MPERF 0x000000E7\r
\r
Msr = AsmReadMsr64 (MSR_IA32_APERF);\r
AsmWriteMsr64 (MSR_IA32_APERF, Msr);\r
@endcode\r
+ @note MSR_IA32_APERF is defined as IA32_APERF in SDM.\r
**/\r
#define MSR_IA32_APERF 0x000000E8\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r
@endcode\r
+ @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.\r
**/\r
#define MSR_IA32_MTRRCAP 0x000000FE\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);\r
AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.\r
**/\r
#define MSR_IA32_SYSENTER_CS 0x00000174\r
\r
Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);\r
AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);\r
@endcode\r
+ @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.\r
**/\r
#define MSR_IA32_SYSENTER_ESP 0x00000175\r
\r
Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);\r
AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);\r
@endcode\r
+ @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.\r
**/\r
#define MSR_IA32_SYSENTER_EIP 0x00000176\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r
@endcode\r
+ @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
**/\r
#define MSR_IA32_MCG_CAP 0x00000179\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);\r
AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.\r
**/\r
#define MSR_IA32_MCG_STATUS 0x0000017A\r
\r
Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);\r
AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);\r
@endcode\r
+ @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.\r
**/\r
#define MSR_IA32_MCG_CTL 0x0000017B\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);\r
AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.\r
+ MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.\r
+ MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.\r
+ MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r
@{\r
**/\r
#define MSR_IA32_PERFEVTSEL0 0x00000186\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);\r
@endcode\r
+ @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.\r
**/\r
#define MSR_IA32_PERF_STATUS 0x00000198\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);\r
AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.\r
**/\r
#define MSR_IA32_PERF_CTL 0x00000199\r
\r
\r
/**\r
Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled\r
- Clock Modulation.". Introduced at Display Family / Display Model 0F_0H.\r
+ Clock Modulation.". If CPUID.01H:EDX[22] = 1.\r
\r
@param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)\r
@param EAX Lower 32-bits of MSR value.\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);\r
AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.\r
**/\r
#define MSR_IA32_CLOCK_MODULATION 0x0000019A\r
\r
UINT32 ExtendedOnDemandClockModulationDutyCycle:1;\r
///\r
/// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded\r
- /// values for target duty cycle modulation.\r
+ /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 OnDemandClockModulationDutyCycle:3;\r
///\r
/// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.\r
+ /// If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 OnDemandClockModulationEnable:1;\r
UINT32 Reserved1:27;\r
Thermal Interrupt Control (R/W) Enables and disables the generation of an\r
interrupt on temperature transitions detected with the processor's thermal\r
sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".\r
- Introduced at Display Family / Display Model 0F_0H.\r
+ If CPUID.01H:EDX[22] = 1\r
\r
@param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)\r
@param EAX Lower 32-bits of MSR value.\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);\r
AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.\r
**/\r
#define MSR_IA32_THERM_INTERRUPT 0x0000019B\r
\r
///\r
struct {\r
///\r
- /// [Bit 0] High-Temperature Interrupt Enable.\r
+ /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 HighTempEnable:1;\r
///\r
- /// [Bit 1] Low-Temperature Interrupt Enable.\r
+ /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 LowTempEnable:1;\r
///\r
- /// [Bit 2] PROCHOT# Interrupt Enable.\r
+ /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 PROCHOT_Enable:1;\r
///\r
- /// [Bit 3] FORCEPR# Interrupt Enable.\r
+ /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 FORCEPR_Enable:1;\r
///\r
/// [Bit 4] Critical Temperature Interrupt Enable.\r
+ /// If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 CriticalTempEnable:1;\r
UINT32 Reserved1:3;\r
///\r
- /// [Bits 14:8] Threshold #1 Value.\r
+ /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 Threshold1:7;\r
///\r
- /// [Bit 15] Threshold #1 Interrupt Enable.\r
+ /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 Threshold1Enable:1;\r
///\r
- /// [Bits 22:16] Threshold #2 Value.\r
+ /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 Threshold2:7;\r
///\r
- /// [Bit 23] Threshold #2 Interrupt Enable.\r
+ /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 Threshold2Enable:1;\r
///\r
/**\r
Thermal Status Information (RO) Contains status information about the\r
processor's thermal sensor and automatic thermal monitoring facilities. See\r
- Section 14.7.2, "Thermal Monitor". Introduced at Display Family / Display\r
- Model 0F_0H.\r
+ Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.\r
\r
@param ECX MSR_IA32_THERM_STATUS (0x0000019C)\r
@param EAX Lower 32-bits of MSR value.\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);\r
@endcode\r
+ @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.\r
**/\r
#define MSR_IA32_THERM_STATUS 0x0000019C\r
\r
///\r
struct {\r
///\r
- /// [Bit 0] Thermal Status (RO):.\r
+ /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 ThermalStatus:1;\r
///\r
- /// [Bit 1] Thermal Status Log (R/W):.\r
+ /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 ThermalStatusLog:1;\r
///\r
- /// [Bit 2] PROCHOT # or FORCEPR# event (RO).\r
+ /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 PROCHOT_FORCEPR_Event:1;\r
///\r
- /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0).\r
+ /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 PROCHOT_FORCEPR_Log:1;\r
///\r
- /// [Bit 4] Critical Temperature Status (RO).\r
+ /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 CriticalTempStatus:1;\r
///\r
/// [Bit 5] Critical Temperature Status log (R/WC0).\r
+ /// If CPUID.01H:EDX[22] = 1.\r
///\r
UINT32 CriticalTempStatusLog:1;\r
///\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);\r
AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
#define MSR_IA32_MISC_ENABLE 0x000001A0\r
\r
/// automatically reduce power consumption in response to TCC activation.\r
/// 0 = Disabled. Note: In some products clearing this bit might be\r
/// ignored in critical thermal conditions, and TM1, TM2 and adaptive\r
- /// thermal throttling will still be activated. Introduced at Display\r
- /// Family / Display Model 0F_0H.\r
+ /// thermal throttling will still be activated. The default value of this\r
+ /// field varies with product. See respective tables where default value is\r
+ /// listed. Introduced at Display Family / Display Model 0F_0H.\r
///\r
UINT32 AutomaticThermalControlCircuit:1;\r
UINT32 Reserved2:3;\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] Precise Event Based Sampling (PEBS) Unavailable (RO) 1 =\r
+ /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =\r
/// PEBS is not supported; 0 = PEBS is supported. Introduced at Display\r
/// Family / Display Model 06_0FH.\r
///\r
UINT32 Reserved6:3;\r
///\r
/// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H\r
- /// returns a maximum value in EAX[7:0] of 3. BIOS should contain a setup\r
+ /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup\r
/// question that allows users to specify when the installed OS does not\r
- /// support CPUID functions greater than 3. Before setting this bit, BIOS\r
+ /// support CPUID functions greater than 2. Before setting this bit, BIOS\r
/// must execute the CPUID.0H and examine the maximum value returned in\r
- /// EAX[7:0]. If the maximum value is greater than 3, the bit is\r
- /// supported. Otherwise, the bit is not supported. Writing to this bit\r
- /// when the maximum value is greater than 3 may generate a #GP exception.\r
+ /// EAX[7:0]. If the maximum value is greater than 2, this bit is\r
+ /// supported. Otherwise, this bit is not supported. Setting this bit when\r
+ /// the maximum value is not greater than 2 may generate a #GP exception.\r
/// Setting this bit may cause unexpected behavior in software that\r
- /// depends on the availability of CPUID leaves greater than 3. Introduced\r
+ /// depends on the availability of CPUID leaves greater than 2. Introduced\r
/// at Display Family / Display Model 0F_03H.\r
///\r
UINT32 LimitCpuidMaxval:1;\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);\r
AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r
**/\r
#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);\r
@endcode\r
+ @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.\r
**/\r
#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);\r
AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.\r
**/\r
#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);\r
AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.\r
**/\r
#define MSR_IA32_DEBUGCTL 0x000001D9\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);\r
AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.\r
**/\r
#define MSR_IA32_SMRR_PHYSBASE 0x000001F2\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);\r
AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.\r
**/\r
#define MSR_IA32_SMRR_PHYSMASK 0x000001F3\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);\r
@endcode\r
+ @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.\r
**/\r
#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8\r
\r
Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);\r
AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);\r
@endcode\r
+ @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.\r
**/\r
#define MSR_IA32_CPU_DCA_CAP 0x000001F9\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);\r
AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.\r
**/\r
#define MSR_IA32_DCA_0_CAP 0x000001FA\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);\r
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.\r
@{\r
**/\r
#define MSR_IA32_MTRR_PHYSBASE0 0x00000200\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);\r
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.\r
@{\r
**/\r
#define MSR_IA32_MTRR_PHYSMASK0 0x00000201\r
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);\r
AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);\r
@endcode\r
+ @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX64K_00000 0x00000250\r
\r
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);\r
AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);\r
@endcode\r
+ @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX16K_80000 0x00000258\r
\r
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);\r
AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);\r
@endcode\r
+ @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259\r
\r
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);\r
AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);\r
@endcode\r
+ @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268\r
\r
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);\r
AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);\r
@endcode\r
+ @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269\r
\r
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);\r
AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);\r
@endcode\r
+ @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A\r
\r
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);\r
AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);\r
@endcode\r
+ @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B\r
\r
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);\r
AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);\r
@endcode\r
+ @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C\r
\r
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);\r
AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);\r
@endcode\r
+ @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D\r
\r
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);\r
AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);\r
@endcode\r
+ @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E\r
\r
Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);\r
AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);\r
@endcode\r
+ @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);\r
AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_PAT is defined as IA32_PAT in SDM.\r
**/\r
#define MSR_IA32_PAT 0x00000277\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);\r
AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM.\r
+ MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM.\r
+ MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM.\r
+ MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM.\r
+ MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.\r
+ MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM.\r
+ MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM.\r
+ MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM.\r
+ MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM.\r
+ MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM.\r
+ MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.\r
+ MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.\r
+ MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.\r
+ MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.\r
+ MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.\r
+ MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.\r
+ MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.\r
+ MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.\r
+ MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.\r
+ MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.\r
+ MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.\r
+ MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.\r
+ MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.\r
+ MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.\r
+ MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.\r
+ MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.\r
+ MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.\r
+ MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.\r
+ MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.\r
+ MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.\r
+ MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.\r
+ MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.\r
@{\r
**/\r
#define MSR_IA32_MC0_CTL2 0x00000280\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.\r
**/\r
#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF\r
\r
Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);\r
AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);\r
@endcode\r
+ @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.\r
**/\r
#define MSR_IA32_FIXED_CTR0 0x00000309\r
\r
\r
/**\r
- Fixed-Function Performance Counter 1 0 (R/W): Counts CPU_CLK_Unhalted.Core.\r
- If CPUID.0AH: EDX[4:0] > 1.\r
+ Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If\r
+ CPUID.0AH: EDX[4:0] > 1.\r
\r
@param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)\r
@param EAX Lower 32-bits of MSR value.\r
Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);\r
AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);\r
@endcode\r
+ @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.\r
**/\r
#define MSR_IA32_FIXED_CTR1 0x0000030A\r
\r
\r
/**\r
- Fixed-Function Performance Counter 0 0 (R/W): Counts CPU_CLK_Unhalted.Ref.\r
- If CPUID.0AH: EDX[4:0] > 2.\r
+ Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If\r
+ CPUID.0AH: EDX[4:0] > 2.\r
\r
@param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)\r
@param EAX Lower 32-bits of MSR value.\r
Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);\r
AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);\r
@endcode\r
+ @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.\r
**/\r
#define MSR_IA32_FIXED_CTR2 0x0000030B\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);\r
AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.\r
**/\r
#define MSR_IA32_PERF_CAPABILITIES 0x00000345\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);\r
AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.\r
**/\r
#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);\r
@endcode\r
+ @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
**/\r
#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);\r
AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.\r
**/\r
#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);\r
AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.\r
**/\r
#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);\r
AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
**/\r
#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);\r
AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r
**/\r
#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);\r
@endcode\r
+ @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.\r
**/\r
#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);\r
AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.\r
**/\r
#define MSR_IA32_PEBS_ENABLE 0x000003F1\r
\r
Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);\r
AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);\r
@endcode\r
+ @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM.\r
+ MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM.\r
+ MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM.\r
+ MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM.\r
+ MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.\r
+ MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM.\r
+ MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM.\r
+ MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM.\r
+ MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM.\r
+ MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM.\r
+ MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.\r
+ MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.\r
+ MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.\r
+ MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.\r
+ MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.\r
+ MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.\r
+ MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.\r
+ MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.\r
+ MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.\r
+ MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.\r
+ MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.\r
+ MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.\r
+ MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.\r
+ MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.\r
+ MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.\r
+ MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.\r
+ MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.\r
+ MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.\r
+ MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.\r
@{\r
**/\r
#define MSR_IA32_MC0_CTL 0x00000400\r
Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);\r
AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);\r
@endcode\r
+ @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM.\r
+ MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM.\r
+ MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM.\r
+ MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM.\r
+ MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM.\r
+ MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM.\r
+ MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM.\r
+ MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM.\r
+ MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM.\r
+ MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM.\r
+ MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.\r
+ MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.\r
+ MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.\r
+ MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.\r
+ MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.\r
+ MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.\r
+ MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.\r
+ MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.\r
+ MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.\r
+ MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.\r
+ MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.\r
+ MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.\r
+ MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.\r
+ MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.\r
+ MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.\r
+ MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.\r
+ MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.\r
+ MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.\r
+ MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.\r
@{\r
**/\r
#define MSR_IA32_MC0_STATUS 0x00000401\r
Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);\r
AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);\r
@endcode\r
+ @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM.\r
+ MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM.\r
+ MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM.\r
+ MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM.\r
+ MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM.\r
+ MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM.\r
+ MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM.\r
+ MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM.\r
+ MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM.\r
+ MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM.\r
+ MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.\r
+ MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.\r
+ MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.\r
+ MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.\r
+ MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.\r
+ MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.\r
+ MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.\r
+ MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.\r
+ MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.\r
+ MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.\r
+ MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.\r
+ MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.\r
+ MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.\r
+ MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.\r
+ MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.\r
+ MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.\r
+ MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.\r
+ MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.\r
+ MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.\r
@{\r
**/\r
#define MSR_IA32_MC0_ADDR 0x00000402\r
Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);\r
AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);\r
@endcode\r
+ @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM.\r
+ MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM.\r
+ MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM.\r
+ MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM.\r
+ MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM.\r
+ MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM.\r
+ MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r
+ MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM.\r
+ MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM.\r
+ MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM.\r
+ MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.\r
+ MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.\r
+ MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.\r
+ MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.\r
+ MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.\r
+ MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.\r
+ MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.\r
+ MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.\r
+ MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.\r
+ MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.\r
+ MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.\r
+ MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.\r
+ MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.\r
+ MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.\r
+ MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.\r
+ MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.\r
+ MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.\r
+ MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.\r
+ MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.\r
@{\r
**/\r
#define MSR_IA32_MC0_MISC 0x00000403\r
\r
<b>Example usage</b>\r
@code\r
- UINT64 Msr;\r
+ MSR_IA32_VMX_BASIC_REGISTER Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_BASIC);\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);\r
@endcode\r
+ @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.\r
**/\r
#define MSR_IA32_VMX_BASIC 0x00000480\r
\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_VMX_BASIC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 30:0] VMCS revision identifier used by the processor. Processors\r
+ /// that use the same VMCS revision identifier use the same size for VMCS\r
+ /// regions (see subsequent item on bits 44:32).\r
+ ///\r
+ /// @note Earlier versions of this manual specified that the VMCS revision\r
+ /// identifier was a 32-bit field in bits 31:0 of this MSR. For all\r
+ /// processors produced prior to this change, bit 31 of this MSR was read\r
+ /// as 0.\r
+ ///\r
+ UINT32 VmcsRevisonId:31;\r
+ UINT32 MustBeZero:1;\r
+ ///\r
+ /// [Bit 44:32] Reports the number of bytes that software should allocate\r
+ /// for the VMXON region and any VMCS region. It is a value greater than\r
+ /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).\r
+ ///\r
+ UINT32 VmcsSize:13;\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bit 48] Indicates the width of the physical addresses that may be used\r
+ /// for the VMXON region, each VMCS, and data structures referenced by\r
+ /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX\r
+ /// transitions). If the bit is 0, these addresses are limited to the\r
+ /// processor's physical-address width. If the bit is 1, these addresses\r
+ /// are limited to 32 bits. This bit is always 0 for processors that\r
+ /// support Intel 64 architecture.\r
+ ///\r
+ /// @note On processors that support Intel 64 architecture, the pointer\r
+ /// must not set bits beyond the processor's physical address width.\r
+ ///\r
+ UINT32 VmcsAddressWidth:1;\r
+ ///\r
+ /// [Bit 49] If bit 49 is read as 1, the logical processor supports the\r
+ /// dual-monitor treatment of system-management interrupts and\r
+ /// system-management mode. See Section 34.15 for details of this treatment.\r
+ ///\r
+ UINT32 DualMonitor:1;\r
+ ///\r
+ /// [Bit 53:50] report the memory type that should be used for the VMCS,\r
+ /// for data structures referenced by pointers in the VMCS (I/O bitmaps,\r
+ /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG\r
+ /// header. If software needs to access these data structures (e.g., to\r
+ /// modify the contents of the MSR bitmaps), it can configure the paging\r
+ /// structures to map them into the linear-address space. If it does so,\r
+ /// it should establish mappings that use the memory type reported bits\r
+ /// 53:50 in this MSR.\r
+ ///\r
+ /// As of this writing, all processors that support VMX operation indicate\r
+ /// the write-back type.\r
+ ///\r
+ /// If software needs to access these data structures (e.g., to modify\r
+ /// the contents of the MSR bitmaps), it can configure the paging\r
+ /// structures to map them into the linear-address space. If it does so,\r
+ /// it should establish mappings that use the memory type reported in this\r
+ /// MSR.\r
+ ///\r
+ /// @note Alternatively, software may map any of these regions or\r
+ /// structures with the UC memory type. (This may be necessary for the MSEG\r
+ /// header.) Doing so is discouraged unless necessary as it will cause the\r
+ /// performance of software accesses to those structures to suffer.\r
+ ///\r
+ ///\r
+ UINT32 MemoryType:4;\r
+ ///\r
+ /// [Bit 54] If bit 54 is read as 1, the processor reports information in\r
+ /// the VM-exit instruction-information field on VM exitsdue to execution\r
+ /// of the INS and OUTS instructions (see Section 27.2.4). This reporting\r
+ /// is done only if this bit is read as 1.\r
+ ///\r
+ UINT32 InsOutsReporting:1;\r
+ ///\r
+ /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may\r
+ /// be cleared to 0. See Appendix A.2 for details. It also reports support\r
+ /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,\r
+ /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and\r
+ /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,\r
+ /// Appendix A.4, and Appendix A.5 for details.\r
+ ///\r
+ UINT32 VmxControls:1;\r
+ UINT32 Reserved2:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_VMX_BASIC_REGISTER;\r
+\r
+///\r
+/// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType\r
+///\r
+#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00\r
+#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06\r
+///\r
+/// @}\r
+///\r
+\r
\r
/**\r
Capability Reporting Register of Pinbased VM-execution Controls (R/O) See\r
\r
Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);\r
@endcode\r
+ @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.\r
**/\r
#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);\r
@endcode\r
+ @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.\r
**/\r
#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);\r
@endcode\r
+ @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.\r
**/\r
#define MSR_IA32_VMX_EXIT_CTLS 0x00000483\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);\r
@endcode\r
+ @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.\r
**/\r
#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484\r
\r
\r
<b>Example usage</b>\r
@code\r
- UINT64 Msr;\r
+ IA32_VMX_MISC_REGISTER Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_MISC);\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);\r
@endcode\r
+ @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.\r
**/\r
#define MSR_IA32_VMX_MISC 0x00000485\r
\r
+/**\r
+ MSR information returned for MSR index #IA32_VMX_MISC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] Reports a value X that specifies the relationship between the\r
+ /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).\r
+ /// Specifically, the VMX-preemption timer (if it is active) counts down by\r
+ /// 1 every time bit X in the TSC changes due to a TSC increment.\r
+ ///\r
+ UINT32 VmxTimerRatio:5;\r
+ ///\r
+ /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA\r
+ /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more\r
+ /// details. This bit is read as 1 on any logical processor that supports\r
+ /// the 1-setting of the "unrestricted guest" VM-execution control.\r
+ ///\r
+ UINT32 VmExitEferLma:1;\r
+ ///\r
+ /// [Bit 6] reports (if set) the support for activity state 1 (HLT).\r
+ ///\r
+ UINT32 HltActivityStateSupported:1;\r
+ ///\r
+ /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).\r
+ ///\r
+ UINT32 ShutdownActivityStateSupported:1;\r
+ ///\r
+ /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).\r
+ ///\r
+ UINT32 WaitForSipiActivityStateSupported:1;\r
+ UINT32 Reserved1:5;\r
+ ///\r
+ /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used\r
+ /// in VMX operation. If the processor supports Intel PT but does not allow\r
+ /// it to be used in VMX operation, execution of VMXON clears\r
+ /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30);\r
+ /// any attempt to set that bit while in VMX operation (including VMX root\r
+ /// operation) using the WRMSR instruction causes a general-protection\r
+ /// exception.\r
+ ///\r
+ UINT32 ProcessorTraceSupported:1;\r
+ ///\r
+ /// [Bit 15] If read as 1, the RDMSR instruction can be used in system-\r
+ /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).\r
+ /// See Section 34.15.6.3.\r
+ ///\r
+ UINT32 SmBaseMsrSupported:1;\r
+ ///\r
+ /// [Bits 24:16] Indicate the number of CR3-target values supported by the\r
+ /// processor. This number is a value between 0 and 256, inclusive (bit 24\r
+ /// is set if and only if bits 23:16 are clear).\r
+ ///\r
+ UINT32 NumberOfCr3TargetValues:9;\r
+ ///\r
+ /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum\r
+ /// number of MSRs that should appear in the VM-exit MSR-store list, the\r
+ /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if\r
+ /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the\r
+ /// recommended maximum number of MSRs to be included in each list. If the\r
+ /// limit is exceeded, undefined processor behavior may result (including a\r
+ /// machine check during the VMX transition).\r
+ ///\r
+ UINT32 MsrStoreListMaximum:3;\r
+ ///\r
+ /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set\r
+ /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1\r
+ /// (see Section 34.14.4).\r
+ ///\r
+ UINT32 BlockSmiSupported:1;\r
+ ///\r
+ /// [Bit 29] read as 1, software can use VMWRITE to write to any supported\r
+ /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit\r
+ /// information fields.\r
+ ///\r
+ UINT32 VmWriteSupported:1;\r
+ ///\r
+ /// [Bit 30] If read as 1, VM entry allows injection of a software\r
+ /// interrupt, software exception, or privileged software exception with an\r
+ /// instruction length of 0.\r
+ ///\r
+ UINT32 VmInjectSupported:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the\r
+ /// processor.\r
+ ///\r
+ UINT32 MsegRevisionIdentifier:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} IA32_VMX_MISC_REGISTER;\r
+\r
\r
/**\r
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,\r
\r
Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);\r
@endcode\r
+ @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.\r
**/\r
#define MSR_IA32_VMX_CR0_FIXED0 0x00000486\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);\r
@endcode\r
+ @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.\r
**/\r
#define MSR_IA32_VMX_CR0_FIXED1 0x00000487\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);\r
@endcode\r
+ @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.\r
**/\r
#define MSR_IA32_VMX_CR4_FIXED0 0x00000488\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);\r
@endcode\r
+ @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.\r
**/\r
#define MSR_IA32_VMX_CR4_FIXED1 0x00000489\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);\r
@endcode\r
+ @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.\r
**/\r
#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);\r
@endcode\r
+ @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.\r
**/\r
#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);\r
@endcode\r
+ @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.\r
**/\r
#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);\r
@endcode\r
+ @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.\r
**/\r
#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);\r
@endcode\r
+ @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.\r
**/\r
#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);\r
@endcode\r
+ @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.\r
**/\r
#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);\r
@endcode\r
+ @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.\r
**/\r
#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);\r
@endcode\r
+ @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.\r
**/\r
#define MSR_IA32_VMX_VMFUNC 0x00000491\r
\r
Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);\r
AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);\r
@endcode\r
+ @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.\r
+ MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.\r
+ MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.\r
+ MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.\r
+ MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.\r
+ MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.\r
+ MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.\r
+ MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.\r
@{\r
**/\r
#define MSR_IA32_A_PMC0 0x000004C1\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);\r
AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.\r
**/\r
#define MSR_IA32_MCG_EXT_CTL 0x000004D0\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);\r
@endcode\r
+ @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.\r
**/\r
#define MSR_IA32_SGX_SVN_STATUS 0x00000500\r
\r
///\r
struct {\r
///\r
- /// [Bit 0] Lock. See Section 42.12.3, "Interactions with Authenticated\r
+ /// [Bit 0] Lock. See Section 42.11.3, "Interactions with Authenticated\r
/// Code Modules (ACMs)".\r
///\r
UINT32 Lock:1;\r
UINT32 Reserved1:15;\r
///\r
- /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.12.3, "Interactions with\r
+ /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.11.3, "Interactions with\r
/// Authenticated Code Modules (ACMs)".\r
///\r
UINT32 SGX_SVN_SINIT:8;\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);\r
AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.\r
**/\r
#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);\r
AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.\r
**/\r
#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r
AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.\r
**/\r
#define MSR_IA32_RTIT_CTL 0x00000570\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);\r
AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.\r
**/\r
#define MSR_IA32_RTIT_STATUS 0x00000571\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);\r
AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.\r
**/\r
#define MSR_IA32_RTIT_CR3_MATCH 0x00000572\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);\r
AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.\r
+ MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.\r
+ MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.\r
+ MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.\r
@{\r
**/\r
#define MSR_IA32_RTIT_ADDR0_A 0x00000580\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);\r
AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.\r
+ MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.\r
+ MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.\r
+ MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.\r
@{\r
**/\r
#define MSR_IA32_RTIT_ADDR0_B 0x00000581\r
/**\r
DS Save Area (R/W) Points to the linear address of the first byte of the DS\r
buffer management area, which is used to manage the BTS and PEBS buffers.\r
- See Section 18.12.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]\r
+ See Section 18.15.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]\r
= 1.\r
\r
[Bits 31..0] The linear address of the first byte of the DS buffer\r
Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);\r
AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);\r
@endcode\r
+ @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.\r
**/\r
#define MSR_IA32_DS_AREA 0x00000600\r
\r
Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);\r
AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);\r
@endcode\r
+ @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.\r
**/\r
#define MSR_IA32_TSC_DEADLINE 0x000006E0\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);\r
AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.\r
**/\r
#define MSR_IA32_PM_ENABLE 0x00000770\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);\r
@endcode\r
+ @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.\r
**/\r
#define MSR_IA32_HWP_CAPABILITIES 0x00000771\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);\r
AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.\r
**/\r
#define MSR_IA32_HWP_REQUEST_PKG 0x00000772\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);\r
AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.\r
**/\r
#define MSR_IA32_HWP_INTERRUPT 0x00000773\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);\r
AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.\r
**/\r
#define MSR_IA32_HWP_REQUEST 0x00000774\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);\r
AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.\r
**/\r
#define MSR_IA32_HWP_STATUS 0x00000777\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);\r
@endcode\r
+ @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.\r
**/\r
#define MSR_IA32_X2APIC_APICID 0x00000802\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);\r
@endcode\r
+ @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.\r
**/\r
#define MSR_IA32_X2APIC_VERSION 0x00000803\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);\r
AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);\r
@endcode\r
+ @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.\r
**/\r
#define MSR_IA32_X2APIC_TPR 0x00000808\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);\r
@endcode\r
+ @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.\r
**/\r
#define MSR_IA32_X2APIC_PPR 0x0000080A\r
\r
Msr = 0;\r
AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);\r
@endcode\r
+ @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.\r
**/\r
#define MSR_IA32_X2APIC_EOI 0x0000080B\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);\r
@endcode\r
+ @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.\r
**/\r
#define MSR_IA32_X2APIC_LDR 0x0000080D\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);\r
AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);\r
@endcode\r
+ @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.\r
**/\r
#define MSR_IA32_X2APIC_SIVR 0x0000080F\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);\r
@endcode\r
+ @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.\r
+ MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.\r
+ MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.\r
+ MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.\r
+ MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.\r
+ MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.\r
+ MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.\r
+ MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.\r
@{\r
**/\r
#define MSR_IA32_X2APIC_ISR0 0x00000810\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);\r
@endcode\r
+ @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.\r
+ MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.\r
+ MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.\r
+ MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.\r
+ MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.\r
+ MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.\r
+ MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.\r
+ MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.\r
@{\r
**/\r
#define MSR_IA32_X2APIC_TMR0 0x00000818\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);\r
@endcode\r
+ @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.\r
+ MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.\r
+ MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.\r
+ MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.\r
+ MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.\r
+ MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.\r
+ MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.\r
+ MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.\r
@{\r
**/\r
#define MSR_IA32_X2APIC_IRR0 0x00000820\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);\r
AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);\r
@endcode\r
+ @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.\r
**/\r
#define MSR_IA32_X2APIC_ESR 0x00000828\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);\r
AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);\r
@endcode\r
+ @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.\r
**/\r
#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);\r
AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);\r
@endcode\r
+ @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.\r
**/\r
#define MSR_IA32_X2APIC_ICR 0x00000830\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);\r
AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);\r
@endcode\r
+ @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.\r
**/\r
#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);\r
AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);\r
@endcode\r
+ @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.\r
**/\r
#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);\r
AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);\r
@endcode\r
+ @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.\r
**/\r
#define MSR_IA32_X2APIC_LVT_PMI 0x00000834\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);\r
AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);\r
@endcode\r
+ @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.\r
**/\r
#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);\r
AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);\r
@endcode\r
+ @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.\r
**/\r
#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);\r
AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);\r
@endcode\r
+ @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.\r
**/\r
#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);\r
AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);\r
@endcode\r
+ @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.\r
**/\r
#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);\r
@endcode\r
+ @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.\r
**/\r
#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839\r
\r
Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);\r
AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);\r
@endcode\r
+ @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.\r
**/\r
#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E\r
\r
Msr = 0;\r
AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);\r
@endcode\r
+ @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.\r
**/\r
#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);\r
AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.\r
**/\r
#define MSR_IA32_DEBUG_INTERFACE 0x00000C80\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);\r
AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.\r
**/\r
#define MSR_IA32_L3_QOS_CFG 0x00000C81\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);\r
AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
**/\r
#define MSR_IA32_QM_EVTSEL 0x00000C8D\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);\r
@endcode\r
+ @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.\r
**/\r
#define MSR_IA32_QM_CTR 0x00000C8E\r
\r
\r
\r
/**\r
- Resource Association Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] =\r
- 1 ).\r
+ Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]\r
+ =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).\r
\r
@param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)\r
@param EAX Lower 32-bits of MSR value.\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);\r
AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
**/\r
#define MSR_IA32_PQR_ASSOC 0x00000C8F\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);\r
AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.\r
**/\r
#define MSR_IA32_BNDCFGS 0x00000D90\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);\r
AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_XSS is defined as IA32_XSS in SDM.\r
**/\r
#define MSR_IA32_XSS 0x00000DA0\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);\r
AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.\r
**/\r
#define MSR_IA32_PKG_HDC_CTL 0x00000DB0\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);\r
AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.\r
**/\r
#define MSR_IA32_PM_CTL1 0x00000DB1\r
\r
\r
Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);\r
@endcode\r
+ @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.\r
**/\r
#define MSR_IA32_THREAD_STALL 0x00000DB2\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);\r
AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_EFER is defined as IA32_EFER in SDM.\r
**/\r
#define MSR_IA32_EFER 0xC0000080\r
\r
Msr = AsmReadMsr64 (MSR_IA32_STAR);\r
AsmWriteMsr64 (MSR_IA32_STAR, Msr);\r
@endcode\r
+ @note MSR_IA32_STAR is defined as IA32_STAR in SDM.\r
**/\r
#define MSR_IA32_STAR 0xC0000081\r
\r
Msr = AsmReadMsr64 (MSR_IA32_LSTAR);\r
AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);\r
@endcode\r
+ @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.\r
**/\r
#define MSR_IA32_LSTAR 0xC0000082\r
\r
Msr = AsmReadMsr64 (MSR_IA32_FMASK);\r
AsmWriteMsr64 (MSR_IA32_FMASK, Msr);\r
@endcode\r
+ @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.\r
**/\r
#define MSR_IA32_FMASK 0xC0000084\r
\r
Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);\r
AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);\r
@endcode\r
+ @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.\r
**/\r
#define MSR_IA32_FS_BASE 0xC0000100\r
\r
Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);\r
AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);\r
@endcode\r
+ @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.\r
**/\r
#define MSR_IA32_GS_BASE 0xC0000101\r
\r
Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);\r
AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);\r
@endcode\r
+ @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.\r
**/\r
#define MSR_IA32_KERNEL_GS_BASE 0xC0000102\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);\r
AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);\r
@endcode\r
+ @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.\r
**/\r
#define MSR_IA32_TSC_AUX 0xC0000103\r
\r
projects / mirror_edk2.git / blobdiff