UefiCpuPkg/Include/Register/Msr: Update reference spec info.

[mirror_edk2.git] / UefiCpuPkg / Include / Register / ArchitecturalMsr.h

diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index 34fdf5be3aec05428b7552c53430c14799d9dfb2..5d2242aa80e4bfdfab501d677c294cd359ef259e 100644 (file)
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not\r
   provided for that MSR.\r
 \r
-  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -16,16 +16,8 @@
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 \r
   @par Specification Reference:\r
-  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
-  September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.1.\r
-\r
-  @par Specification Reference:\r
-  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
-  September 2016, Appendix A VMX Capability Reporting Facility, Section A.1.\r
-\r
-  @par Specification Reference:\r
-  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
-  September 2016, Appendix A VMX Capability Reporting Facility, Section A.6.\r
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+  May 2018, Volume 4: Model-Specific-Registers (MSR)\r
 \r
 **/\r
 \r
@@ -33,7 +25,7 @@
 #define __ARCHITECTURAL_MSR_H__\r
 \r
 /**\r
-  See Section 35.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r
+  See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r
 \r
   @param  ECX  MSR_IA32_P5_MC_ADDR (0x00000000)\r
   @param  EAX  Lower 32-bits of MSR value.\r
@@ -52,7 +44,7 @@
 \r
 \r
 /**\r
-  See Section 35.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r
+  See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r
 \r
   @param  ECX  MSR_IA32_P5_MC_TYPE (0x00000001)\r
   @param  EAX  Lower 32-bits of MSR value.\r
@@ -91,7 +83,7 @@
 \r
 \r
 /**\r
-  See Section 17.15, "Time-Stamp Counter.". Introduced at Display Family /\r
+  See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /\r
   Display Model 05_01H.\r
 \r
   @param  ECX  MSR_IA32_TIME_STAMP_COUNTER (0x00000010)\r
@@ -493,9 +485,8 @@ typedef union {
     UINT32  Valid:1;\r
     UINT32  Reserved1:1;\r
     ///\r
-    /// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the\r
-    /// default treatment of SMIs and SMM.  Executions of VMXOFF unblock SMIs\r
-    /// unless bit 2 is 1 (the value of bit 0 is irrelevant).\r
+    /// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If\r
+    /// IA32_VMX_MISC[28].\r
     ///\r
     UINT32  BlockSmi:1;\r
     UINT32  Reserved2:9;\r
@@ -1953,7 +1944,7 @@ typedef union {
 \r
 \r
 /**\r
-  SMRR Range Mask. (Writeable only in SMM)  Range Mask of SMM memory range. If\r
+  SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If\r
   IA32_MTRRCAP[SMRR] = 1.\r
 \r
   @param  ECX  MSR_IA32_SMRR_PHYSMASK (0x000001F3)\r
@@ -4417,13 +4408,13 @@ typedef union {
   ///\r
   struct {\r
     ///\r
-    /// [Bit 0] Lock. See Section 42.11.3, "Interactions with Authenticated\r
+    /// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated\r
     /// Code Modules (ACMs)".\r
     ///\r
     UINT32  Lock:1;\r
     UINT32  Reserved1:15;\r
     ///\r
-    /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.11.3, "Interactions with\r
+    /// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with\r
     /// Authenticated Code Modules (ACMs)".\r
     ///\r
     UINT32  SGX_SVN_SINIT:8;\r
@@ -4925,16 +4916,11 @@ typedef union {
 \r
 \r
 /**\r
-  DS Save Area (R/W)  Points to the linear address of the first byte of the DS\r
+  DS Save Area (R/W) Points to the linear address of the first byte of the DS\r
   buffer management area, which is used to manage the BTS and PEBS buffers.\r
-  See Section 18.15.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]\r
-  = 1.\r
-\r
-    [Bits 31..0] The linear address of the first byte of the DS buffer\r
-    management area, if not in IA-32e mode.\r
-\r
-    [Bits 63..0] The linear address of the first byte of the DS buffer\r
-    management area, if IA-32e mode is active.\r
+  See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If(\r
+  CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS\r
+  buffer management area, if IA-32e mode is active.\r
 \r
   @param  ECX  MSR_IA32_DS_AREA (0x00000600)\r
   @param  EAX  Lower 32-bits of MSR value.\r