UefiCpuPkg/Include/Register/Msr: Update reference spec info.

[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / AtomMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
index b2764690f55b47a4cb13dd1d9ec338697d9d65e1..2025b652933d87da70c949be2a70bda81f7a4920 100644 (file)
--- a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not\r
   provided for that MSR.\r
 \r
-  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -16,8 +16,8 @@
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 \r
   @par Specification Reference:\r
-  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
-  September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.3.\r
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+  May 2018, Volume 4: Model-Specific-Registers (MSR)\r
 \r
 **/\r
 \r
@@ -518,18 +518,18 @@ typedef union {
   ///\r
   struct {\r
     ///\r
-    /// [Bit 0] Fast-Strings Enable See Table 35-2.\r
+    /// [Bit 0] Fast-Strings Enable See Table 2-2.\r
     ///\r
     UINT32  FastStrings:1;\r
     UINT32  Reserved1:2;\r
     ///\r
     /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
-    /// Table 35-2. Default value is 0.\r
+    /// Table 2-2. Default value is 0.\r
     ///\r
     UINT32  AutomaticThermalControlCircuit:1;\r
     UINT32  Reserved2:3;\r
     ///\r
-    /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.\r
+    /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.\r
     ///\r
     UINT32  PerformanceMonitoring:1;\r
     UINT32  Reserved3:1;\r
@@ -542,12 +542,12 @@ typedef union {
     ///\r
     UINT32  FERR:1;\r
     ///\r
-    /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.\r
+    /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
     ///\r
     UINT32  BTS:1;\r
     ///\r
     /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r
-    /// Table 35-2.\r
+    /// Table 2-2.\r
     ///\r
     UINT32  PEBS:1;\r
     ///\r
@@ -568,12 +568,12 @@ typedef union {
     UINT32  Reserved5:2;\r
     ///\r
     /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
-    /// Table 35-2.\r
+    /// Table 2-2.\r
     ///\r
     UINT32  EIST:1;\r
     UINT32  Reserved6:1;\r
     ///\r
-    /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.\r
+    /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
     ///\r
     UINT32  MONITOR:1;\r
     UINT32  Reserved7:1;\r
@@ -588,17 +588,17 @@ typedef union {
     UINT32  EISTLock:1;\r
     UINT32  Reserved8:1;\r
     ///\r
-    /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 35-2.\r
+    /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2.\r
     ///\r
     UINT32  LimitCpuidMaxval:1;\r
     ///\r
-    /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.\r
+    /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r
     ///\r
     UINT32  xTPR_Message_Disable:1;\r
     UINT32  Reserved9:8;\r
     UINT32  Reserved10:2;\r
     ///\r
-    /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.\r
+    /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r
     ///\r
     UINT32  XD:1;\r
     UINT32  Reserved11:29;\r
@@ -673,7 +673,7 @@ typedef union {
 \r
 \r
 /**\r
-  Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling\r
+  Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
   (PEBS).".\r
 \r
   @param  ECX  MSR_ATOM_PEBS_ENABLE (0x000003F1)\r