UefiCpuPkg/Include/Register/Msr: Update reference spec info.

[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / HaswellMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
index 3cd15846b4fd2e19d8eb64d01c5265589faa52f3..3e748a16698500c16c883b8389044f52dae0d99e 100644 (file)
--- a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not\r
   provided for that MSR.\r
 \r
-  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -16,8 +16,8 @@
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 \r
   @par Specification Reference:\r
-  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
-  September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.11.\r
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+  May 2018, Volume 4: Model-Specific-Registers (MSR)\r
 \r
 **/\r
 \r
@@ -129,8 +129,8 @@ typedef union {
 \r
 \r
 /**\r
-  THREAD. Performance Event Select for Counter n (R/W) Supports all fields\r
-  described inTable 35-2 and the fields below.\r
+  Thread. Performance Event Select for Counter n (R/W) Supports all fields\r
+  described inTable 2-2 and the fields below.\r
 \r
   @param  ECX  MSR_HASWELL_IA32_PERFEVTSELn\r
   @param  EAX  Lower 32-bits of MSR value.\r
@@ -218,7 +218,7 @@ typedef union {
     UINT32  CMASK:8;\r
     UINT32  Reserved:32;\r
     ///\r
-    /// [Bit 32] IN_TX: see Section 18.11.5.1 When IN_TX (bit 32) is set,\r
+    /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,\r
     /// AnyThread (bit 21) should be cleared to prevent incorrect results.\r
     ///\r
     UINT32  IN_TX:1;\r
@@ -232,8 +232,8 @@ typedef union {
 \r
 \r
 /**\r
-  THREAD. Performance Event Select for Counter 2 (R/W) Supports all fields\r
-  described inTable 35-2 and the fields below.\r
+  Thread. Performance Event Select for Counter 2 (R/W) Supports all fields\r
+  described inTable 2-2 and the fields below.\r
 \r
   @param  ECX  MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188)\r
   @param  EAX  Lower 32-bits of MSR value.\r
@@ -314,12 +314,12 @@ typedef union {
     UINT32  CMASK:8;\r
     UINT32  Reserved:32;\r
     ///\r
-    /// [Bit 32] IN_TX: see Section 18.11.5.1 When IN_TX (bit 32) is set,\r
+    /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,\r
     /// AnyThread (bit 21) should be cleared to prevent incorrect results.\r
     ///\r
     UINT32  IN_TX:1;\r
     ///\r
-    /// [Bit 33] IN_TXCP: see Section 18.11.5.1 When IN_TXCP=1 & IN_TX=1 and\r
+    /// [Bit 33] IN_TXCP: see Section 18.3.6.5.1 When IN_TXCP=1 & IN_TX=1 and\r
     /// in sampling, spurious PMI may occur and transactions may continuously\r
     /// abort near overflow conditions. Software should favor using IN_TXCP\r
     /// for counting over sampling. If sampling, software should use large\r
@@ -459,9 +459,9 @@ typedef union {
     ///\r
     UINT32  InterruptResponseTimeLimit:10;\r
     ///\r
-    /// [Bits 12:10] Time Unit (R/W)  Specifies the encoding value of time\r
-    /// unit of the interrupt response time limit. See Table 35-18 for\r
-    /// supported time unit encodings.\r
+    /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
+    /// of the interrupt response time limit. See Table 2-19 for supported\r
+    /// time unit encodings.\r
     ///\r
     UINT32  TimeUnit:3;\r
     UINT32  Reserved1:2;\r
@@ -518,15 +518,15 @@ typedef union {
   ///\r
   struct {\r
     ///\r
-    /// [Bits 9:0] Interrupt response time limit (R/W)  Specifies the limit\r
+    /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
     /// that should be used to decide if the package should be put into a\r
     /// package C6 or C7 state.\r
     ///\r
     UINT32  InterruptResponseTimeLimit:10;\r
     ///\r
-    /// [Bits 12:10] Time Unit (R/W)  Specifies the encoding value of time\r
-    /// unit of the interrupt response time limit. See Table 35-18 for\r
-    /// supported time unit encodings.\r
+    /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
+    /// of the interrupt response time limit. See Table 2-19 for supported\r
+    /// time unit encodings.\r
     ///\r
     UINT32  TimeUnit:3;\r
     UINT32  Reserved1:2;\r