UefiCpuPkg/Include/Register/Msr: Update reference spec info.

[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / IvyBridgeMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
index 39b0d1af12f92f982a9afc3e511076053877e49d..f45b538ea7087ba44b599d78d03fa5a723f5320c 100644 (file)
--- a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not\r
   provided for that MSR.\r
 \r
-  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -16,8 +16,8 @@
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 \r
   @par Specification Reference:\r
-  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
-  September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.10.\r
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+  May 2018, Volume 4: Model-Specific-Registers (MSR)\r
 \r
 **/\r
 \r
@@ -1112,7 +1112,7 @@ typedef union {
 \r
 \r
 /**\r
-  Thread. See Section 18.8.1.1, "Precise Event Based Sampling (PEBS).".\r
+  Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r
 \r
   @param  ECX  MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)\r
   @param  EAX  Lower 32-bits of MSR value.\r