returned is a single 32-bit or 64-bit value, then a data structure is not\r
provided for that MSR.\r
\r
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
@par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.18.\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
///\r
struct {\r
///\r
- /// [Bit 0] Fast-Strings Enable. See Table 35-2.\r
+ /// [Bit 0] Fast-Strings Enable. See Table 2-2.\r
///\r
UINT32 FastStrings:1;\r
UINT32 Reserved1:1;\r
UINT32 FPU:1;\r
///\r
/// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal\r
- /// Monitor," and see Table 35-2.\r
+ /// Monitor," and see Table 2-2.\r
///\r
UINT32 TM1:1;\r
///\r
///\r
UINT32 ThirdLevelCacheDisable:1;\r
///\r
- /// [Bit 7] Performance Monitoring Available (R) See Table 35-2.\r
+ /// [Bit 7] Performance Monitoring Available (R) See Table 2-2.\r
///\r
UINT32 PerformanceMonitoring:1;\r
///\r
UINT32 FERR:1;\r
///\r
/// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See\r
- /// Table 35-2. When set, the processor does not support branch trace\r
+ /// Table 2-2. When set, the processor does not support branch trace\r
/// storage (BTS); when clear, BTS is supported.\r
///\r
UINT32 BTS:1;\r
///\r
/// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable\r
- /// (R) See Table 35-2. When set, the processor does not support processor\r
+ /// (R) See Table 2-2. When set, the processor does not support processor\r
/// event-based sampling (PEBS); when clear, PEBS is supported.\r
///\r
UINT32 PEBS:1;\r
UINT32 TM2:1;\r
UINT32 Reserved3:4;\r
///\r
- /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 35-2.\r
+ /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
UINT32 MONITOR:1;\r
///\r
UINT32 AdjacentCacheLinePrefetchDisable:1;\r
UINT32 Reserved4:2;\r
///\r
- /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 35-2. Setting\r
- /// this can cause unexpected behavior to software that depends on the\r
+ /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 2-2. Setting this\r
+ /// can cause unexpected behavior to software that depends on the\r
/// availability of CPUID leaves greater than 3.\r
///\r
UINT32 LimitCpuidMaxval:1;\r
///\r
- /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.\r
+ /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
UINT32 xTPR_Message_Disable:1;\r
///\r
UINT32 Reserved5:7;\r
UINT32 Reserved6:2;\r
///\r
- /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.\r
+ /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r
///\r
UINT32 XD:1;\r
UINT32 Reserved7:29;\r
0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains\r
a pointer to the last branch instruction that the processor executed prior\r
to the last exception that was generated or the last interrupt that was\r
- handled. See Section 17.11.3, "Last Exception Records.". Unique. From Linear\r
- IP Linear address of the last branch instruction (If IA32e mode is active).\r
+ handled. See Section 17.13.3, "Last Exception Records.". Unique. From Linear\r
+ IP Linear address of the last branch instruction (If IA-32e mode is active).\r
From Linear IP Linear address of the last branch instruction. Reserved.\r
\r
@param ECX MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7)\r
0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area\r
contains a pointer to the target of the last branch instruction that the\r
processor executed prior to the last exception that was generated or the\r
- last interrupt that was handled. See Section 17.11.3, "Last Exception\r
+ last interrupt that was handled. See Section 17.13.3, "Last Exception\r
Records.". Unique. From Linear IP Linear address of the target of the last\r
branch instruction (If IA-32e mode is active). From Linear IP Linear address\r
of the target of the last branch instruction. Reserved.\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug\r
features are used. Bit definitions are discussed in the referenced section.\r
- See Section 17.11.1, "MSR_DEBUGCTLA MSR.".\r
+ See Section 17.13.1, "MSR_DEBUGCTLA MSR.".\r
\r
@param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)\r
@param EAX Lower 32-bits of MSR value.\r
0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an\r
index (0-3 or 0-15) that points to the top of the last branch record stack\r
(that is, that points the index of the MSR containing the most recent branch\r
- record). See Section 17.11.2, "LBR Stack for Processors Based on Intel\r
+ record). See Section 17.13.2, "LBR Stack for Processors Based on Intel\r
NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.\r
\r
@param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)\r
exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through\r
MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models\r
0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See\r
- Section 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording\r
+ Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording\r
for Processors based on Skylake Microarchitecture.".\r
\r
@param ECX MSR_PENTIUM_4_LASTBRANCH_n\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
\r
@param ECX MSR_PENTIUM_4_BPU_COUNTERn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
\r
@param ECX MSR_PENTIUM_4_MS_COUNTERn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
\r
@param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
\r
@param ECX MSR_PENTIUM_4_IQ_COUNTERn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_BPU_CCCRn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_MS_CCCRn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_FLAME_CCCRn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_IQ_CCCRn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2. Shared. See Section 18.15.1, "ESCR MSRs." This MSR is not available\r
- on later processors. It is only available on processor family 0FH, models\r
- 01H-02H.\r
+ 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not\r
+ available on later processors. It is only available on processor family 0FH,\r
+ models 01H-02H.\r
\r
@param ECX MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2. Shared. See Section 18.15.1, "ESCR MSRs." This MSR is not available\r
- on later processors. It is only available on processor family 0FH, models\r
- 01H-02H.\r
+ 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not\r
+ available on later processors. It is only available on processor family 0FH,\r
+ models 01H-02H.\r
\r
@param ECX MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_ALF_ESCRn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)\r
@param EAX Lower 32-bits of MSR value.\r
///\r
struct {\r
///\r
- /// [Bits 12:0] See Table 19-33.\r
+ /// [Bits 12:0] See Table 19-36.\r
///\r
UINT32 EventNum:13;\r
UINT32 Reserved1:11;\r
///\r
/// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical\r
/// processor when set; disables PEBS when clear (default). See Section\r
- /// 18.16.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r
+ /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r
/// logical processor. This bit is called ENABLE_PEBS in IA-32 processors\r
/// that do not support Intel HyperThreading Technology.\r
///\r
///\r
/// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical\r
/// processor when set; disables PEBS when clear (default). See Section\r
- /// 18.16.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r
+ /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r
/// logical processor. This bit is reserved for IA-32 processors that do\r
/// not support Intel Hyper-Threading Technology.\r
///\r
\r
\r
/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Table 19-33.\r
+ 0, 1, 2, 3, 4, 6. Shared. See Table 19-36.\r
\r
@param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)\r
@param EAX Lower 32-bits of MSR value.\r
680H-68FH, 6C0H-6CfH are not available in processor releases before family\r
0FH, model 03H. These MSRs replace MSRs previously located at\r
1DBH-1DEH.which performed the same function for early releases. See Section\r
- 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording for\r
+ 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for\r
Processors based on Skylake Microarchitecture.".\r
\r
@param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP\r
record registers on the last branch record stack (6C0H-6CFH). This part of\r
the stack contains pointers to the destination instruction for one of the\r
last 16 branches, exceptions, or interrupts that the processor took. See\r
- Section 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording\r
+ Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording\r
for Processors based on Skylake Microarchitecture.".\r
\r
@param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP\r
\r
\r
/**\r
- 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See\r
- Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP\r
- with Up to 8-MByte L3 Cache.".\r
+ 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See Section\r
+ 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to\r
+ 8-MByte L3 Cache.".\r
\r
@param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See\r
- Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP\r
- with Up to 8-MByte L3 Cache.".\r
+ 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See Section\r
+ 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to\r
+ 8-MByte L3 Cache.".\r
\r
@param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See\r
- Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP\r
- with Up to 8-MByte L3 Cache" for details.\r
+ 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See Section\r
+ 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to\r
+ 8-MByte L3 Cache.".\r
\r
@param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.21,\r
- "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte\r
- L3 Cache" for details.\r
+ 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.6.6,\r
+ "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte\r
+ L3 Cache.".\r
\r
@param ECX MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.21,\r
- "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte\r
+ 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.6.6,\r
+ "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte\r
L3 Cache.".\r
\r
@param ECX MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3)\r
\r
\r
/**\r
- 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section 18.21,\r
- "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte\r
- L3 Cache.".\r
+ 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section\r
+ 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to\r
+ 8MByte L3 Cache.".\r
\r
@param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section\r
- 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to\r
- 8-MByte L3 Cache.".\r
+ 6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section\r
+ 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to\r
+ 8MByte L3 Cache.".\r
\r
@param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.21,\r
- "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte\r
- L3 Cache" for details.\r
+ 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.6.6,\r
+ "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte\r
+ L3 Cache.".\r
\r
@param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0)\r
@param EAX Lower 32-bits of MSR value.\r
projects / mirror_edk2.git / blobdiff