+++ /dev/null
-/** @file\r
- MSR Definitions for Pentium M Processors.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __PENTIUM_M_MSR_H__\r
-#define __PENTIUM_M_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Pentium M Processors?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x0D \\r
- ) \\r
- )\r
-\r
-/**\r
- See Section 2.22, "MSRs in Pentium Processors.".\r
-\r
- @param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000\r
-\r
-\r
-/**\r
- See Section 2.22, "MSRs in Pentium Processors.".\r
-\r
- @param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001\r
-\r
-\r
-/**\r
- Processor Hard Power-On Configuration (R/W) Enables and disables processor\r
- features. (R) Indicates current processor configuration.\r
-\r
- @param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);\r
- @endcode\r
- @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the\r
- /// Pentium M processor.\r
- ///\r
- UINT32 DataErrorCheckingEnable:1;\r
- ///\r
- /// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on\r
- /// the Pentium M processor.\r
- ///\r
- UINT32 ResponseErrorCheckingEnable:1;\r
- ///\r
- /// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium\r
- /// M processor.\r
- ///\r
- UINT32 MCERR_DriveEnable:1;\r
- ///\r
- /// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium\r
- /// M processor.\r
- ///\r
- UINT32 AddressParityEnable:1;\r
- UINT32 Reserved2:2;\r
- ///\r
- /// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on\r
- /// the Pentium M processor.\r
- ///\r
- UINT32 BINIT_DriverEnable:1;\r
- ///\r
- /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
- ///\r
- UINT32 OutputTriStateEnable:1;\r
- ///\r
- /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
- ///\r
- UINT32 ExecuteBIST:1;\r
- ///\r
- /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
- /// Always 0 on the Pentium M processor.\r
- ///\r
- UINT32 MCERR_ObservationEnabled:1;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
- /// Always 0 on the Pentium M processor.\r
- ///\r
- UINT32 BINIT_ObservationEnabled:1;\r
- UINT32 Reserved4:1;\r
- ///\r
- /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes\r
- /// Always 0 on the Pentium M processor.\r
- ///\r
- UINT32 ResetVector:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M\r
- /// processor.\r
- ///\r
- UINT32 APICClusterID:2;\r
- ///\r
- /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always\r
- /// 0 on the Pentium M processor.\r
- ///\r
- UINT32 SystemBusFrequency:1;\r
- UINT32 Reserved6:1;\r
- ///\r
- /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium\r
- /// M processor.\r
- ///\r
- UINT32 SymmetricArbitrationID:2;\r
- ///\r
- /// [Bits 26:22] Clock Frequency Ratio (R/O).\r
- ///\r
- UINT32 ClockFrequencyRatio:5;\r
- UINT32 Reserved7:5;\r
- UINT32 Reserved8:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER;\r
-\r
-\r
-/**\r
- Last Branch Record n (R/W) One of 8 last branch record registers on the last\r
- branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold\r
- the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section\r
- 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M\r
- Processors)".\r
-\r
- @param ECX MSR_PENTIUM_M_LASTBRANCH_n\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.\r
- MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.\r
- MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.\r
- MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r
- MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.\r
- MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.\r
- MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.\r
- MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.\r
- @{\r
-**/\r
-#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040\r
-#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041\r
-#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042\r
-#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043\r
-#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044\r
-#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045\r
-#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046\r
-#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047\r
-/// @}\r
-\r
-\r
-/**\r
- Reserved.\r
-\r
- @param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);\r
- @endcode\r
- @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
- /// Indicates if the L2 is hardware-disabled.\r
- ///\r
- UINT32 L2HardwareEnabled:1;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the\r
- /// cache data bus. ECC is always generated on write cycles. 1. = Disabled\r
- /// (default) 2. = Enabled For the Pentium M processor, ECC checking on\r
- /// the cache data bus is always enabled.\r
- ///\r
- UINT32 ECCCheckEnable:1;\r
- UINT32 Reserved2:2;\r
- ///\r
- /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =\r
- /// Disabled (default) Until this bit is set the processor will not\r
- /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
- ///\r
- UINT32 L2Enabled:1;\r
- UINT32 Reserved3:14;\r
- ///\r
- /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
- ///\r
- UINT32 L2NotPresent:1;\r
- UINT32 Reserved4:8;\r
- UINT32 Reserved5:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER;\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:16;\r
- ///\r
- /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
- /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
- /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r
- /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
- /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.\r
- ///\r
- UINT32 TM_SELECT:1;\r
- UINT32 Reserved2:15;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_PENTIUM_M_THERM2_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Enable Miscellaneous Processor Features (R/W) Allows a variety of processor\r
- functions to be enabled and disabled.\r
-\r
- @param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:3;\r
- ///\r
- /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting\r
- /// this bit enables the thermal control circuit (TCC) portion of the\r
- /// Intel Thermal Monitor feature. This allows processor clocks to be\r
- /// automatically modulated based on the processor's thermal sensor\r
- /// operation. 0 = Disabled (default). The automatic thermal control\r
- /// circuit enable bit determines if the thermal control circuit (TCC)\r
- /// will be activated when the processor's internal thermal sensor\r
- /// determines the processor is about to exceed its maximum operating\r
- /// temperature. When the TCC is activated and TM1 is enabled, the\r
- /// processors clocks will be forced to a 50% duty cycle. BIOS must enable\r
- /// this feature. The bit should not be confused with the on-demand\r
- /// thermal control circuit enable bit.\r
- ///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bit 7] Performance Monitoring Available (R) 1 = Performance\r
- /// monitoring enabled 0 = Performance monitoring disabled.\r
- ///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:2;\r
- ///\r
- /// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the\r
- /// processor to indicate a pending break event within the processor 0 =\r
- /// Indicates compatible FERR# signaling behavior This bit must be set to\r
- /// 1 to support XAPIC interrupt model usage.\r
- /// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't\r
- /// support branch trace storage (BTS) 0 = BTS is supported\r
- ///\r
- UINT32 FERR:1;\r
- ///\r
- /// [Bit 11] Branch Trace Storage Unavailable (RO)\r
- /// 1 = Processor doesn't support branch trace storage (BTS)\r
- /// 0 = BTS is supported\r
- ///\r
- UINT32 BTS:1;\r
- ///\r
- /// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =\r
- /// Processor does not support processor event based sampling (PEBS); 0 =\r
- /// PEBS is supported. The Pentium M processor does not support PEBS.\r
- ///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved5:3;\r
- ///\r
- /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =\r
- /// Enhanced Intel SpeedStep Technology enabled. On the Pentium M\r
- /// processor, this bit may be configured to be read-only.\r
- ///\r
- UINT32 EIST:1;\r
- UINT32 Reserved6:6;\r
- ///\r
- /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r
- /// disabled. xTPR messages are optional messages that allow the processor\r
- /// to inform the chipset of its priority. The default is processor\r
- /// specific.\r
- ///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points\r
- to the MSR containing the most recent branch record. See also: -\r
- MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt,\r
- and Exception Recording (Pentium M Processors)".\r
-\r
- @param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9\r
-\r
-\r
-/**\r
- Debug Control (R/W) Controls how several debug features are used. Bit\r
- definitions are discussed in the referenced section. See Section 17.15,\r
- "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".\r
-\r
- @param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9\r
-\r
-\r
-/**\r
- Last Exception Record To Linear IP (R) This area contains a pointer to the\r
- target of the last branch instruction that the processor executed prior to\r
- the last exception that was generated or the last interrupt that was\r
- handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording\r
- (Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception\r
- MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);\r
- @endcode\r
- @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD\r
-\r
-\r
-/**\r
- Last Exception Record From Linear IP (R) Contains a pointer to the last\r
- branch instruction that the processor executed prior to the last exception\r
- that was generated or the last interrupt that was handled. See Section\r
- 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M\r
- Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);\r
- @endcode\r
- @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE\r
-\r
-\r
-/**\r
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_MC4_CTL 0x0000040C\r
-\r
-\r
-/**\r
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D\r
-\r
-\r
-/**\r
- See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is\r
- either not implemented or contains no address if the ADDRV flag in the\r
- MSR_MC4_STATUS register is clear. When not implemented in the processor, all\r
- reads and writes to this MSR will cause a general-protection exception.\r
-\r
- @param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E\r
-\r
-\r
-/**\r
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_MC3_CTL 0x00000410\r
-\r
-\r
-/**\r
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_MC3_STATUS 0x00000411\r
-\r
-\r
-/**\r
- See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is\r
- either not implemented or contains no address if the ADDRV flag in the\r
- MSR_MC3_STATUS register is clear. When not implemented in the processor, all\r
- reads and writes to this MSR will cause a general-protection exception.\r
-\r
- @param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_MC3_ADDR 0x00000412\r
-\r
-#endif\r
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