returned is a single 32-bit or 64-bit value, then a data structure is not\r
provided for that MSR.\r
\r
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
@par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.22.\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
\r
\r
/**\r
- See Section 17.15, "Time-Stamp Counter.".\r
+ See Section 17.17, "Time-Stamp Counter.".\r
\r
@param ECX MSR_PENTIUM_TSC (0x00000010)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- See Section 18.24.1, "Control and Event Select Register (CESR).".\r
+ See Section 18.6.9.1, "Control and Event Select Register (CESR).".\r
\r
@param ECX MSR_PENTIUM_CESR (0x00000011)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Section 18.24.3, "Events Counted.".\r
+ Section 18.6.9.3, "Events Counted.".\r
\r
@param ECX MSR_PENTIUM_CTRn\r
@param EAX Lower 32-bits of MSR value.\r