returned is a single 32-bit or 64-bit value, then a data structure is not\r
provided for that MSR.\r
\r
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
@par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.9.\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
\r
\r
/**\r
- Package. See http://biosbits.org.\r
+ Package. Platform Information Contains power management and other model\r
+ specific features enumeration. See http://biosbits.org.\r
\r
@param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Core. See Table 35-2; If CPUID.0AH:EAX[15:8] = 8.\r
+ Core. See Table 2-2. If CPUID.0AH:EAX[15:8] = 8.\r
\r
@param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Thread. Clock Modulation (R/W) See Table 35-2 IA32_CLOCK_MODULATION MSR was\r
+ Thread. Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was\r
originally named IA32_THERM_CONTROL MSR.\r
\r
@param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A)\r
///\r
struct {\r
///\r
- /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.\r
+ /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.\r
///\r
UINT32 FastStrings:1;\r
UINT32 Reserved1:6;\r
///\r
- /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.\r
+ /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.\r
///\r
UINT32 PerformanceMonitoring:1;\r
UINT32 Reserved2:3;\r
///\r
- /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.\r
+ /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
///\r
UINT32 BTS:1;\r
///\r
/// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See\r
- /// Table 35-2.\r
+ /// Table 2-2.\r
///\r
UINT32 PEBS:1;\r
UINT32 Reserved3:3;\r
///\r
/// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
- /// Table 35-2.\r
+ /// Table 2-2.\r
///\r
UINT32 EIST:1;\r
UINT32 Reserved4:1;\r
///\r
- /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.\r
+ /// [Bit 18] Thread. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
UINT32 MONITOR:1;\r
UINT32 Reserved5:3;\r
///\r
- /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.\r
+ /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.\r
///\r
UINT32 LimitCpuidMaxval:1;\r
///\r
- /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.\r
+ /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
UINT32 xTPR_Message_Disable:1;\r
UINT32 Reserved6:8;\r
UINT32 Reserved7:2;\r
///\r
- /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.\r
+ /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.\r
///\r
UINT32 XD:1;\r
UINT32 Reserved8:3;\r
\r
\r
/**\r
- Thread. Last Branch Record Filtering Select Register (R/W) See Section\r
- 17.7.2, "Filtering of Last Branch Records.".\r
+ Thread. Last Branch Record Filtering Select Register (R/W) See Section\r
+ 17.9.2, "Filtering of Last Branch Records.".\r
\r
@param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".\r
+ See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
\r
@param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
+ Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control\r
Facilities.".\r
\r
@param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F)\r
\r
\r
/**\r
- See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".\r
+ See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
\r
@param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Thread. See Section 18.8.1.1, "Processor Event Based Sampling (PEBS).".\r
+ Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r
\r
@param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Thread. see See Section 18.8.1.2, "Load Latency Performance Monitoring\r
+ Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring\r
Facility.".\r
\r
@param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)\r
\r
\r
/**\r
- Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.\r
+ Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r
\r
@param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r
@param EAX Lower 32-bits of MSR value.\r
///\r
/// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS\r
/// counting logic for specific events requiring additional configuration,\r
- /// see Table 19-15.\r
+ /// see Table 19-17.\r
///\r
UINT32 ENABLE_PEBS_NUM_ALT:1;\r
UINT32 Reserved1:31;\r
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