returned is a single 32-bit or 64-bit value, then a data structure is not\r
provided for that MSR.\r
\r
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
@par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6.\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
+/**\r
+ Is Intel(R) Xeon(R) Processor Series 5600?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x25 || \\r
+ DisplayModel == 0x2C \\r
+ ) \\r
+ )\r
+\r
/**\r
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
handler to handle unsuccessful read of this MSR.\r
\r
\r
/**\r
- Package. See Table 35-2.\r
+ Package. See Table 2-2.\r
\r
@param ECX MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)\r
@param EAX Lower 32-bits of MSR value.\r