UefiCpuPkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / Xeon5600Msr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
index a4c6ba0845640daca908bb8c24be1e90bcbddccd..c285d1877f53329d9ddb65098fc4d06feea6f475 100644 (file)
--- a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
@@ -6,18 +6,12 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not\r
   provided for that MSR.\r
 \r
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
-  This program and the accompanying materials\r
-  are licensed and made available under the terms and conditions of the BSD License\r
-  which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
   @par Specification Reference:\r
-  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
-  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6.\r
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+  May 2018, Volume 4: Model-Specific-Registers (MSR)\r
 \r
 **/\r
 \r
@@ -26,6 +20,23 @@
 \r
 #include <Register/ArchitecturalMsr.h>\r
 \r
+/**\r
+  Is Intel(R) Xeon(R) Processor Series 5600?\r
+\r
+  @param   DisplayFamily  Display Family ID\r
+  @param   DisplayModel   Display Model ID\r
+\r
+  @retval  TRUE   Yes, it is.\r
+  @retval  FALSE  No, it isn't.\r
+**/\r
+#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \\r
+  (DisplayFamily == 0x06 && \\r
+   (                        \\r
+    DisplayModel == 0x25 || \\r
+    DisplayModel == 0x2C    \\r
+    )                       \\r
+   )\r
+\r
 /**\r
   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
   handler to handle unsuccessful read of this MSR.\r
@@ -43,6 +54,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);\r
   AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);\r
   @endcode\r
+  @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
 **/\r
 #define MSR_XEON_5600_FEATURE_CONFIG             0x0000013C\r
 \r
@@ -92,6 +104,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);\r
   AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);\r
   @endcode\r
+  @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
 **/\r
 #define MSR_XEON_5600_OFFCORE_RSP_1              0x000001A7\r
 \r
@@ -112,6 +125,7 @@ typedef union {
 \r
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);\r
   @endcode\r
+  @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
 **/\r
 #define MSR_XEON_5600_TURBO_RATIO_LIMIT          0x000001AD\r
 \r
@@ -163,7 +177,7 @@ typedef union {
 \r
 \r
 /**\r
-  Package. See Table 35-2.\r
+  Package. See Table 2-2.\r
 \r
   @param  ECX  MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)\r
   @param  EAX  Lower 32-bits of MSR value.\r
@@ -176,6 +190,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);\r
   AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);\r
   @endcode\r
+  @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r
 **/\r
 #define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS      0x000001B0\r
 \r