UefiCpuPkg/Include/Register/Msr: Update reference spec info.

[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / XeonDMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
index 7b31288a353340f1e72110284068e34404533d9c..cf013ea887514fb7f932033ca963da29307a262c 100644 (file)
--- a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not\r
   provided for that MSR.\r
 \r
-  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -16,8 +16,8 @@
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 \r
   @par Specification Reference:\r
-  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
-  September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.14.\r
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+  May 2018, Volume 4: Model-Specific-Registers (MSR)\r
 \r
 **/\r
 \r
@@ -72,11 +72,11 @@ typedef union {
   ///\r
   struct {\r
     ///\r
-    /// [Bit 0] LockOut (R/WO) See Table 35-24.\r
+    /// [Bit 0] LockOut (R/WO) See Table 2-25.\r
     ///\r
     UINT32  LockOut:1;\r
     ///\r
-    /// [Bit 1] Enable_PPIN (R/W) See Table 35-24.\r
+    /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.\r
     ///\r
     UINT32  Enable_PPIN:1;\r
     UINT32  Reserved1:30;\r
@@ -95,7 +95,7 @@ typedef union {
 \r
 /**\r
   Package. Protected Processor Inventory Number (R/O). Protected Processor\r
-  Inventory Number (R/O) See Table 35-24.\r
+  Inventory Number (R/O) See Table 2-25.\r
 \r
   @param  ECX  MSR_XEON_D_PPIN (0x0000004F)\r
   @param  EAX  Lower 32-bits of MSR value.\r
@@ -142,33 +142,33 @@ typedef union {
   struct {\r
     UINT32  Reserved1:8;\r
     ///\r
-    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 35-24.\r
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.\r
     ///\r
     UINT32  MaximumNonTurboRatio:8;\r
     UINT32  Reserved2:7;\r
     ///\r
-    /// [Bit 23] Package. PPIN_CAP (R/O) See Table 35-24.\r
+    /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.\r
     ///\r
     UINT32  PPIN_CAP:1;\r
     UINT32  Reserved3:4;\r
     ///\r
     /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
-    /// Table 35-24.\r
+    /// Table 2-25.\r
     ///\r
     UINT32  RatioLimit:1;\r
     ///\r
     /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
-    /// Table 35-24.\r
+    /// Table 2-25.\r
     ///\r
     UINT32  TDPLimit:1;\r
     ///\r
-    /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 35-24.\r
+    /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.\r
     ///\r
     UINT32  TJOFFSET:1;\r
     UINT32  Reserved4:1;\r
     UINT32  Reserved5:8;\r
     ///\r
-    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 35-24.\r
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.\r
     ///\r
     UINT32  MaximumEfficiencyRatio:8;\r
     UINT32  Reserved6:16;\r
@@ -434,11 +434,11 @@ typedef union {
   struct {\r
     UINT32  Reserved1:16;\r
     ///\r
-    /// [Bits 23:16] Temperature Target (RO) See Table 35-24.\r
+    /// [Bits 23:16] Temperature Target (RO) See Table 2-25.\r
     ///\r
     UINT32  TemperatureTarget:8;\r
     ///\r
-    /// [Bits 27:24] TCC Activation Offset (R/W) See Table 35-24.\r
+    /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.\r
     ///\r
     UINT32  TCCActivationOffset:4;\r
     UINT32  Reserved2:4;\r