UefiCpuPkg/Include: Update MSR header files with SDM (Sep.2016)

[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / XeonE7Msr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
index b95f963b1ed13f56766f78449684229e35b84199..d14ef21d6f123c5e9f1a9c09a1e5ae7ef6ddc2f6 100644 (file)
--- a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
@@ -17,7 +17,7 @@
 \r
   @par Specification Reference:\r
   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
-  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-7.\r
+  September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.8.\r
 \r
 **/\r
 \r
@@ -26,6 +26,78 @@
 \r
 #include <Register/ArchitecturalMsr.h>\r
 \r
+/**\r
+  Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
+  handler to handle unsuccessful read of this MSR.\r
+\r
+  @param  ECX  MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_XEON_E7_FEATURE_CONFIG_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);\r
+  AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);\r
+  @endcode\r
+  @note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
+**/\r
+#define MSR_XEON_E7_FEATURE_CONFIG               0x0000013C\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    ///\r
+    /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this\r
+    /// MSR, the configuration of AES instruction set availability is as\r
+    /// follows: 11b: AES instructions are not available until next RESET.\r
+    /// otherwise, AES instructions are available. Note, AES instruction set\r
+    /// is not available if read is unsuccessful. If the configuration is not\r
+    /// 01b, AES instruction can be mis-configured if a privileged agent\r
+    /// unintentionally writes 11b.\r
+    ///\r
+    UINT32  AESConfiguration:2;\r
+    UINT32  Reserved1:30;\r
+    UINT32  Reserved2:32;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 32-bit value\r
+  ///\r
+  UINT32  Uint32;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+  Thread. Offcore Response Event Select Register (R/W).\r
+\r
+  @param  ECX  MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);\r
+  AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);\r
+  @endcode\r
+  @note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
+**/\r
+#define MSR_XEON_E7_OFFCORE_RSP_1                0x000001A7\r
+\r
+\r
 /**\r
   Package. Reserved Attempt to read/write will cause #UD.\r
 \r
@@ -40,6 +112,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);\r
   AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
 **/\r
 #define MSR_XEON_E7_TURBO_RATIO_LIMIT            0x000001AD\r
 \r
@@ -58,6 +131,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);\r
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.\r
 **/\r
 #define MSR_XEON_E7_C8_PMON_BOX_CTRL             0x00000F40\r
 \r
@@ -76,6 +150,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);\r
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r
 **/\r
 #define MSR_XEON_E7_C8_PMON_BOX_STATUS           0x00000F41\r
 \r
@@ -94,6 +169,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);\r
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.\r
 **/\r
 #define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL         0x00000F42\r
 \r
@@ -112,6 +188,12 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);\r
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.\r
+        MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.\r
+        MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.\r
+        MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.\r
+        MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.\r
+        MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.\r
   @{\r
 **/\r
 #define MSR_XEON_E7_C8_PMON_EVNT_SEL0            0x00000F50\r
@@ -137,6 +219,12 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);\r
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
+        MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
+        MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
+        MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
+        MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.\r
+        MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.\r
   @{\r
 **/\r
 #define MSR_XEON_E7_C8_PMON_CTR0                 0x00000F51\r
@@ -162,6 +250,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);\r
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.\r
 **/\r
 #define MSR_XEON_E7_C9_PMON_BOX_CTRL             0x00000FC0\r
 \r
@@ -180,6 +269,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);\r
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r
 **/\r
 #define MSR_XEON_E7_C9_PMON_BOX_STATUS           0x00000FC1\r
 \r
@@ -198,6 +288,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);\r
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.\r
 **/\r
 #define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL         0x00000FC2\r
 \r
@@ -216,6 +307,12 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);\r
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.\r
+        MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.\r
+        MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.\r
+        MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.\r
+        MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.\r
+        MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.\r
   @{\r
 **/\r
 #define MSR_XEON_E7_C9_PMON_EVNT_SEL0            0x00000FD0\r
@@ -241,6 +338,12 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);\r
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
+        MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
+        MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
+        MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
+        MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.\r
+        MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.\r
   @{\r
 **/\r
 #define MSR_XEON_E7_C9_PMON_CTR0                 0x00000FD1\r