\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-15.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.17.\r
\r
**/\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);\r
@endcode\r
+ @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
**/\r
#define MSR_XEON_PHI_SMI_COUNT 0x00000034\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);\r
AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);\r
@endcode\r
+ @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);\r
AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
@endcode\r
+ @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);\r
AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
@endcode\r
+ @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
**/\r
#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);\r
AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);\r
@endcode\r
+ @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
**/\r
#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C\r
\r
} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;\r
\r
\r
+/**\r
+ THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
+ Enhancement. Accessible only while in SMM.\r
+\r
+ @param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
+**/\r
+#define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:26;\r
+ ///\r
+ /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
+ /// SMM code access restriction is supported and a host-space interface\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 SMM_Code_Access_Chk:1;\r
+ ///\r
+ /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
+ /// SMM long flow indicator is supported and a host-space interface\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 Long_Flow_Indication:1;\r
+ UINT32 Reserved3:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_SMM_MCA_CAP_REGISTER;\r
+\r
+\r
/**\r
Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);\r
AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);\r
@endcode\r
+ @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0\r
\r
UINT32 FastStrings:1;\r
UINT32 Reserved1:2;\r
///\r
- /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W).\r
+ /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value\r
+ /// is 1.\r
///\r
UINT32 AutomaticThermalControlCircuit:1;\r
UINT32 Reserved2:3;\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] Precise Event Based Sampling Unavailable (RO).\r
+ /// [Bit 12] Processor Event Based Sampling Unavailable (RO).\r
///\r
UINT32 PEBS:1;\r
UINT32 Reserved4:3;\r
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);\r
AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);\r
@endcode\r
+ @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
**/\r
#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2\r
\r
} MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;\r
\r
\r
+/**\r
+ Miscellaneous Feature Control (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
+**/\r
+#define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the\r
+ /// L1 data cache prefetcher.\r
+ ///\r
+ UINT32 DCUHardwarePrefetcherDisable:1;\r
+ ///\r
+ /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
+ /// L2 hardware prefetcher.\r
+ ///\r
+ UINT32 L2HardwarePrefetcherDisable:1;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER;\r
+\r
+\r
/**\r
Shared. Offcore Response Event Select Register (R/W).\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);\r
AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
**/\r
#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);\r
AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
**/\r
#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);\r
AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);\r
@endcode\r
+ @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);\r
AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
**/\r
#define MSR_XEON_PHI_LBR_SELECT 0x000001C8\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);\r
AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9\r
\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);\r
@endcode\r
+ @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD\r
\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);\r
@endcode\r
+ @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE\r
\r
\r
-/**\r
- Thread. See Table 35-2.\r
-\r
- @param ECX MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS);\r
- AsmWriteMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS, Msr);\r
- @endcode\r
-**/\r
-#define MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
-\r
-\r
/**\r
Thread. See Table 35-2.\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);\r
AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);\r
AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
**/\r
#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);\r
AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
**/\r
#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);\r
AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r
**/\r
#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);\r
AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.\r
**/\r
#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);\r
AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.\r
**/\r
#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);\r
AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
**/\r
#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF\r
\r
\r
-/**\r
- Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_XEON_PHI_MC3_CTL (0x0000040C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_CTL);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC3_CTL, Msr);\r
- @endcode\r
-**/\r
-#define MSR_XEON_PHI_MC3_CTL 0x0000040C\r
-\r
-\r
-/**\r
- Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_XEON_PHI_MC3_STATUS (0x0000040D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_STATUS);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC3_STATUS, Msr);\r
- @endcode\r
-**/\r
-#define MSR_XEON_PHI_MC3_STATUS 0x0000040D\r
-\r
-\r
-/**\r
- Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".\r
-\r
- @param ECX MSR_XEON_PHI_MC3_ADDR (0x0000040E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_ADDR);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC3_ADDR, Msr);\r
- @endcode\r
-**/\r
-#define MSR_XEON_PHI_MC3_ADDR 0x0000040E\r
-\r
-\r
-/**\r
- Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_XEON_PHI_MC4_CTL (0x00000410)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_CTL);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC4_CTL, Msr);\r
- @endcode\r
-**/\r
-#define MSR_XEON_PHI_MC4_CTL 0x00000410\r
-\r
-\r
-/**\r
- Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_XEON_PHI_MC4_STATUS (0x00000411)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_STATUS);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC4_STATUS, Msr);\r
- @endcode\r
-**/\r
-#define MSR_XEON_PHI_MC4_STATUS 0x00000411\r
-\r
-\r
-/**\r
- Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register\r
- is either not implemented or contains no address if the ADDRV flag in the\r
- MSR_MC4_STATUS register is clear. When not implemented in the processor, all\r
- reads and writes to this MSR will cause a general-protection exception.\r
-\r
- @param ECX MSR_XEON_PHI_MC4_ADDR (0x00000412)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_ADDR);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC4_ADDR, Msr);\r
- @endcode\r
-**/\r
-#define MSR_XEON_PHI_MC4_ADDR 0x00000412\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_XEON_PHI_MC5_CTL (0x00000414)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_CTL);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC5_CTL, Msr);\r
- @endcode\r
-**/\r
-#define MSR_XEON_PHI_MC5_CTL 0x00000414\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_XEON_PHI_MC5_STATUS (0x00000415)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_STATUS);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC5_STATUS, Msr);\r
- @endcode\r
-**/\r
-#define MSR_XEON_PHI_MC5_STATUS 0x00000415\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".\r
-\r
- @param ECX MSR_XEON_PHI_MC5_ADDR (0x00000416)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_ADDR);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC5_ADDR, Msr);\r
- @endcode\r
-**/\r
-#define MSR_XEON_PHI_MC5_ADDR 0x00000416\r
-\r
-\r
/**\r
Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.\r
\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);\r
@endcode\r
+ @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r
**/\r
#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);\r
@endcode\r
+ @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.\r
**/\r
#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);\r
@endcode\r
+ @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);\r
AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
**/\r
#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);\r
AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
**/\r
#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610\r
\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);\r
@endcode\r
+ @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611\r
\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);\r
@endcode\r
+ @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
**/\r
#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);\r
AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
**/\r
#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);\r
AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
**/\r
#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618\r
\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);\r
@endcode\r
+ @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619\r
\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);\r
@endcode\r
+ @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);\r
AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
**/\r
#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);\r
AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r
**/\r
#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638\r
\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);\r
@endcode\r
+ @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639\r
\r
\r
/**\r
- Package. Base TDP Ratio (R/O) See Table 35-20.\r
+ Package. Base TDP Ratio (R/O) See Table 35-23.\r
\r
@param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)\r
@param EAX Lower 32-bits of MSR value.\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);\r
@endcode\r
+ @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r
**/\r
#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648\r
\r
\r
/**\r
- Package. ConfigTDP Level 1 ratio and power level (R/O). See Table 35-20.\r
+ Package. ConfigTDP Level 1 ratio and power level (R/O). See Table 35-23.\r
\r
@param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)\r
@param EAX Lower 32-bits of MSR value.\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);\r
@endcode\r
+ @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r
**/\r
#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649\r
\r
\r
/**\r
- Package. ConfigTDP Level 2 ratio and power level (R/O). See Table 35-20.\r
+ Package. ConfigTDP Level 2 ratio and power level (R/O). See Table 35-23.\r
\r
@param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)\r
@param EAX Lower 32-bits of MSR value.\r
\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);\r
@endcode\r
+ @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r
**/\r
#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A\r
\r
\r
/**\r
- Package. ConfigTDP Control (R/W) See Table 35-20.\r
+ Package. ConfigTDP Control (R/W) See Table 35-23.\r
\r
@param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)\r
@param EAX Lower 32-bits of MSR value.\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);\r
AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r
**/\r
#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B\r
\r
\r
/**\r
- Package. ConfigTDP Control (R/W) See Table 35-20.\r
+ Package. ConfigTDP Control (R/W) See Table 35-23.\r
\r
@param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)\r
@param EAX Lower 32-bits of MSR value.\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);\r
AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);\r
@endcode\r
+ @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
**/\r
#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);\r
AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
@endcode\r
+ @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
**/\r
#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690\r
\r
projects / mirror_edk2.git / blobdiff