/** @file\r
CPU MP Initialize Library common functions.\r
\r
- Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2020, AMD Inc. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
EFI_GUID mCpuInitMpLibHobGuid = CPU_INIT_MP_LIB_HOB_GUID;\r
\r
+/**\r
+ Save the volatile registers required to be restored following INIT IPI.\r
+\r
+ @param[out] VolatileRegisters Returns buffer saved the volatile resisters\r
+**/\r
+VOID\r
+SaveVolatileRegisters (\r
+ OUT CPU_VOLATILE_REGISTERS *VolatileRegisters\r
+ );\r
+\r
+/**\r
+ Restore the volatile registers following INIT IPI.\r
+\r
+ @param[in] VolatileRegisters Pointer to volatile resisters\r
+ @param[in] IsRestoreDr TRUE: Restore DRx if supported\r
+ FALSE: Do not restore DRx\r
+**/\r
+VOID\r
+RestoreVolatileRegisters (\r
+ IN CPU_VOLATILE_REGISTERS *VolatileRegisters,\r
+ IN BOOLEAN IsRestoreDr\r
+ );\r
+\r
/**\r
The function will check if BSP Execute Disable is enabled.\r
\r
CPU_MP_DATA *DataInHob;\r
\r
DataInHob = (CPU_MP_DATA *)Buffer;\r
+ //\r
+ // Save and restore volatile registers when switch BSP\r
+ //\r
+ SaveVolatileRegisters (&DataInHob->APInfo.VolatileRegisters);\r
AsmExchangeRole (&DataInHob->APInfo, &DataInHob->BSPInfo);\r
+ RestoreVolatileRegisters (&DataInHob->APInfo.VolatileRegisters, FALSE);\r
}\r
\r
/**\r
//\r
WakeUpAP (CpuMpData, FALSE, ProcessorNumber, FutureBSPProc, CpuMpData, TRUE);\r
\r
+ //\r
+ // Save and restore volatile registers when switch BSP\r
+ //\r
+ SaveVolatileRegisters (&CpuMpData->BSPInfo.VolatileRegisters);\r
AsmExchangeRole (&CpuMpData->BSPInfo, &CpuMpData->APInfo);\r
+ RestoreVolatileRegisters (&CpuMpData->BSPInfo.VolatileRegisters, FALSE);\r
\r
//\r
// Set the BSP bit of MSR_IA32_APIC_BASE on new BSP\r