/** @file\r
CPU MP Initialize Library common functions.\r
\r
- Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2020, AMD Inc. All rights reserved.<BR>\r
+\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "MpLib.h"\r
+#include <Library/VmgExitLib.h>\r
+#include <Register/Amd/Fam17Msr.h>\r
+#include <Register/Amd/Ghcb.h>\r
\r
EFI_GUID mCpuInitMpLibHobGuid = CPU_INIT_MP_LIB_HOB_GUID;\r
\r
+\r
/**\r
The function will check if BSP Execute Disable is enabled.\r
\r
//\r
ApLoopMode = ApInHltLoop;\r
}\r
+\r
+ if (PcdGetBool (PcdSevEsIsEnabled)) {\r
+ //\r
+ // For SEV-ES, force AP in Hlt-loop mode in order to use the GHCB\r
+ // protocol for starting APs\r
+ //\r
+ ApLoopMode = ApInHltLoop;\r
+ }\r
}\r
\r
if (ApLoopMode != ApInMwaitLoop) {\r
)\r
{\r
CPU_MP_DATA *CpuMpData;\r
+ UINTN ProcessorNumber;\r
+ EFI_STATUS Status;\r
\r
CpuMpData = (CPU_MP_DATA *) Buffer;\r
+ Status = GetProcessorNumber (CpuMpData, &ProcessorNumber);\r
+ ASSERT_EFI_ERROR (Status);\r
//\r
// Load microcode on AP\r
//\r
- MicrocodeDetect (CpuMpData, FALSE);\r
+ MicrocodeDetect (CpuMpData, ProcessorNumber);\r
//\r
// Sync BSP's MTRR table to AP\r
//\r
)\r
{\r
UINTN Index;\r
+ CPU_INFO_IN_HOB *CpuInfoInHob;\r
+ BOOLEAN X2Apic;\r
\r
//\r
// Send 1st broadcast IPI to APs to wakeup APs\r
//\r
- CpuMpData->InitFlag = ApInitConfig;\r
- CpuMpData->X2ApicEnable = FALSE;\r
+ CpuMpData->InitFlag = ApInitConfig;\r
WakeUpAP (CpuMpData, TRUE, 0, NULL, NULL, TRUE);\r
CpuMpData->InitFlag = ApInitDone;\r
ASSERT (CpuMpData->CpuCount <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
CpuPause ();\r
}\r
\r
+\r
+ //\r
+ // Enable x2APIC mode if\r
+ // 1. Number of CPU is greater than 255; or\r
+ // 2. There are any logical processors reporting an Initial APIC ID of 255 or greater.\r
+ //\r
+ X2Apic = FALSE;\r
if (CpuMpData->CpuCount > 255) {\r
//\r
// If there are more than 255 processor found, force to enable X2APIC\r
//\r
- CpuMpData->X2ApicEnable = TRUE;\r
+ X2Apic = TRUE;\r
+ } else {\r
+ CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
+ for (Index = 0; Index < CpuMpData->CpuCount; Index++) {\r
+ if (CpuInfoInHob[Index].InitialApicId >= 0xFF) {\r
+ X2Apic = TRUE;\r
+ break;\r
+ }\r
+ }\r
}\r
- if (CpuMpData->X2ApicEnable) {\r
+\r
+ if (X2Apic) {\r
DEBUG ((DEBUG_INFO, "Force x2APIC mode!\n"));\r
//\r
// Wakeup all APs to enable x2APIC mode\r
IN UINT64 ApTopOfStack\r
)\r
{\r
- CPU_INFO_IN_HOB *CpuInfoInHob;\r
+ CPU_INFO_IN_HOB *CpuInfoInHob;\r
+ MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr;\r
\r
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
CpuInfoInHob[ProcessorNumber].InitialApicId = GetInitialApicId ();\r
\r
CpuMpData->CpuData[ProcessorNumber].Waiting = FALSE;\r
CpuMpData->CpuData[ProcessorNumber].CpuHealthy = (BistData == 0) ? TRUE : FALSE;\r
- if (CpuInfoInHob[ProcessorNumber].InitialApicId >= 0xFF) {\r
- //\r
- // Set x2APIC mode if there are any logical processor reporting\r
- // an Initial APIC ID of 255 or greater.\r
- //\r
- AcquireSpinLock(&CpuMpData->MpLock);\r
- CpuMpData->X2ApicEnable = TRUE;\r
- ReleaseSpinLock(&CpuMpData->MpLock);\r
+\r
+ //\r
+ // NOTE: PlatformId is not relevant on AMD platforms.\r
+ //\r
+ if (!StandardSignatureIsAuthenticAMD ()) {\r
+ PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);\r
+ CpuMpData->CpuData[ProcessorNumber].PlatformId = (UINT8)PlatformIdMsr.Bits.PlatformId;\r
}\r
\r
+ AsmCpuid (\r
+ CPUID_VERSION_INFO,\r
+ &CpuMpData->CpuData[ProcessorNumber].ProcessorSignature,\r
+ NULL,\r
+ NULL,\r
+ NULL\r
+ );\r
+\r
InitializeSpinLock(&CpuMpData->CpuData[ProcessorNumber].ApLock);\r
SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle);\r
}\r
\r
+/**\r
+ Get Protected mode code segment with 16-bit default addressing\r
+ from current GDT table.\r
+\r
+ @return Protected mode 16-bit code segment value.\r
+**/\r
+STATIC\r
+UINT16\r
+GetProtectedMode16CS (\r
+ VOID\r
+ )\r
+{\r
+ IA32_DESCRIPTOR GdtrDesc;\r
+ IA32_SEGMENT_DESCRIPTOR *GdtEntry;\r
+ UINTN GdtEntryCount;\r
+ UINT16 Index;\r
+\r
+ Index = (UINT16) -1;\r
+ AsmReadGdtr (&GdtrDesc);\r
+ GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);\r
+ GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;\r
+ for (Index = 0; Index < GdtEntryCount; Index++) {\r
+ if (GdtEntry->Bits.L == 0 &&\r
+ GdtEntry->Bits.DB == 0 &&\r
+ GdtEntry->Bits.Type > 8) {\r
+ break;\r
+ }\r
+ GdtEntry++;\r
+ }\r
+ ASSERT (Index != GdtEntryCount);\r
+ return Index * 8;\r
+}\r
+\r
+/**\r
+ Get Protected mode code segment with 32-bit default addressing\r
+ from current GDT table.\r
+\r
+ @return Protected mode 32-bit code segment value.\r
+**/\r
+STATIC\r
+UINT16\r
+GetProtectedMode32CS (\r
+ VOID\r
+ )\r
+{\r
+ IA32_DESCRIPTOR GdtrDesc;\r
+ IA32_SEGMENT_DESCRIPTOR *GdtEntry;\r
+ UINTN GdtEntryCount;\r
+ UINT16 Index;\r
+\r
+ Index = (UINT16) -1;\r
+ AsmReadGdtr (&GdtrDesc);\r
+ GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);\r
+ GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;\r
+ for (Index = 0; Index < GdtEntryCount; Index++) {\r
+ if (GdtEntry->Bits.L == 0 &&\r
+ GdtEntry->Bits.DB == 1 &&\r
+ GdtEntry->Bits.Type > 8) {\r
+ break;\r
+ }\r
+ GdtEntry++;\r
+ }\r
+ ASSERT (Index != GdtEntryCount);\r
+ return Index * 8;\r
+}\r
+\r
+/**\r
+ Reset an AP when in SEV-ES mode.\r
+\r
+ If successful, this function never returns.\r
+\r
+ @param[in] Ghcb Pointer to the GHCB\r
+ @param[in] CpuMpData Pointer to CPU MP Data\r
+\r
+**/\r
+STATIC\r
+VOID\r
+MpInitLibSevEsAPReset (\r
+ IN GHCB *Ghcb,\r
+ IN CPU_MP_DATA *CpuMpData\r
+ )\r
+{\r
+ UINT16 Code16, Code32;\r
+ AP_RESET *APResetFn;\r
+ UINTN BufferStart;\r
+ UINTN StackStart;\r
+\r
+ Code16 = GetProtectedMode16CS ();\r
+ Code32 = GetProtectedMode32CS ();\r
+\r
+ if (CpuMpData->WakeupBufferHigh != 0) {\r
+ APResetFn = (AP_RESET *) (CpuMpData->WakeupBufferHigh + CpuMpData->AddressMap.SwitchToRealNoNxOffset);\r
+ } else {\r
+ APResetFn = (AP_RESET *) (CpuMpData->MpCpuExchangeInfo->BufferStart + CpuMpData->AddressMap.SwitchToRealOffset);\r
+ }\r
+\r
+ BufferStart = CpuMpData->MpCpuExchangeInfo->BufferStart;\r
+ StackStart = CpuMpData->SevEsAPResetStackStart -\r
+ (AP_RESET_STACK_SIZE * GetApicId ());\r
+\r
+ //\r
+ // This call never returns.\r
+ //\r
+ APResetFn (BufferStart, Code16, Code32, StackStart);\r
+}\r
+\r
/**\r
This function will be called from AP reset code if BSP uses WakeUpAP.\r
\r
ApTopOfStack = CpuMpData->Buffer + (ProcessorNumber + 1) * CpuMpData->CpuApStackSize;\r
BistData = *(UINT32 *) ((UINTN) ApTopOfStack - sizeof (UINTN));\r
//\r
- // Do some AP initialize sync\r
- //\r
- ApInitializeSync (CpuMpData);\r
- //\r
// CpuMpData->CpuData[0].VolatileRegisters is initialized based on BSP environment,\r
// to initialize AP in InitConfig path.\r
// NOTE: IDTR.BASE stored in CpuMpData->CpuData[0].VolatileRegisters points to a different IDT shared by all APs.\r
InitializeApData (CpuMpData, ProcessorNumber, BistData, ApTopOfStack);\r
ApStartupSignalBuffer = CpuMpData->CpuData[ProcessorNumber].StartupApSignal;\r
\r
- InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeInfo->NumApsExecuting);\r
+ //\r
+ // Delay decrementing the APs executing count when SEV-ES is enabled\r
+ // to allow the APs to issue an AP_RESET_HOLD before the BSP possibly\r
+ // performs another INIT-SIPI-SIPI sequence.\r
+ //\r
+ if (!CpuMpData->SevEsIsEnabled) {\r
+ InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeInfo->NumApsExecuting);\r
+ }\r
} else {\r
//\r
// Execute AP function if AP is ready\r
WAKEUP_AP_SIGNAL,\r
0\r
);\r
- if (CpuMpData->ApLoopMode == ApInHltLoop) {\r
- //\r
- // Restore AP's volatile registers saved\r
- //\r
- RestoreVolatileRegisters (&CpuMpData->CpuData[ProcessorNumber].VolatileRegisters, TRUE);\r
- } else {\r
+\r
+ if (CpuMpData->InitFlag == ApInitReconfig) {\r
//\r
- // The CPU driver might not flush TLB for APs on spot after updating\r
- // page attributes. AP in mwait loop mode needs to take care of it when\r
- // woken up.\r
+ // ApInitReconfig happens when:\r
+ // 1. AP is re-enabled after it's disabled, in either PEI or DXE phase.\r
+ // 2. AP is initialized in DXE phase.\r
+ // In either case, use the volatile registers value derived from BSP.\r
+ // NOTE: IDTR.BASE stored in CpuMpData->CpuData[0].VolatileRegisters points to a\r
+ // different IDT shared by all APs.\r
//\r
- CpuFlushTlb ();\r
+ RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters, FALSE);\r
+ } else {\r
+ if (CpuMpData->ApLoopMode == ApInHltLoop) {\r
+ //\r
+ // Restore AP's volatile registers saved before AP is halted\r
+ //\r
+ RestoreVolatileRegisters (&CpuMpData->CpuData[ProcessorNumber].VolatileRegisters, TRUE);\r
+ } else {\r
+ //\r
+ // The CPU driver might not flush TLB for APs on spot after updating\r
+ // page attributes. AP in mwait loop mode needs to take care of it when\r
+ // woken up.\r
+ //\r
+ CpuFlushTlb ();\r
+ }\r
}\r
\r
if (GetApState (&CpuMpData->CpuData[ProcessorNumber]) == CpuStateReady) {\r
//\r
while (TRUE) {\r
DisableInterrupts ();\r
- CpuSleep ();\r
+ if (CpuMpData->SevEsIsEnabled) {\r
+ MSR_SEV_ES_GHCB_REGISTER Msr;\r
+ GHCB *Ghcb;\r
+ UINT64 Status;\r
+ BOOLEAN DoDecrement;\r
+\r
+ DoDecrement = (BOOLEAN) (CpuMpData->InitFlag == ApInitConfig);\r
+\r
+ while (TRUE) {\r
+ Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);\r
+ Ghcb = Msr.Ghcb;\r
+\r
+ VmgInit (Ghcb);\r
+\r
+ if (DoDecrement) {\r
+ DoDecrement = FALSE;\r
+\r
+ //\r
+ // Perform the delayed decrement just before issuing the first\r
+ // VMGEXIT with AP_RESET_HOLD.\r
+ //\r
+ InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeInfo->NumApsExecuting);\r
+ }\r
+\r
+ Status = VmgExit (Ghcb, SVM_EXIT_AP_RESET_HOLD, 0, 0);\r
+ if ((Status == 0) && (Ghcb->SaveArea.SwExitInfo2 != 0)) {\r
+ VmgDone (Ghcb);\r
+ break;\r
+ }\r
+\r
+ VmgDone (Ghcb);\r
+ }\r
+\r
+ //\r
+ // Awakened in a new phase? Use the new CpuMpData\r
+ //\r
+ if (CpuMpData->NewCpuMpData != NULL) {\r
+ CpuMpData = CpuMpData->NewCpuMpData;\r
+ }\r
+\r
+ MpInitLibSevEsAPReset (Ghcb, CpuMpData);\r
+ } else {\r
+ CpuSleep ();\r
+ }\r
CpuPause ();\r
}\r
}\r
ExchangeInfo->Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);\r
DEBUG ((DEBUG_INFO, "%a: 5-Level Paging = %d\n", gEfiCallerBaseName, ExchangeInfo->Enable5LevelPaging));\r
\r
+ ExchangeInfo->SevEsIsEnabled = CpuMpData->SevEsIsEnabled;\r
+ ExchangeInfo->GhcbBase = (UINTN) CpuMpData->GhcbBase;\r
+\r
//\r
// Get the BSP's data of GDT and IDT\r
//\r
// EfiBootServicesCode to avoid page fault if NX memory protection is enabled.\r
//\r
if (CpuMpData->WakeupBufferHigh != 0) {\r
- Size = CpuMpData->AddressMap.RendezvousFunnelSize -\r
- CpuMpData->AddressMap.ModeTransitionOffset;\r
+ Size = CpuMpData->AddressMap.RendezvousFunnelSize +\r
+ CpuMpData->AddressMap.SwitchToRealSize -\r
+ CpuMpData->AddressMap.ModeTransitionOffset;\r
CopyMem (\r
(VOID *)CpuMpData->WakeupBufferHigh,\r
CpuMpData->AddressMap.RendezvousFunnelAddress +\r
CopyMem (\r
(VOID *) CpuMpData->WakeupBuffer,\r
(VOID *) CpuMpData->AddressMap.RendezvousFunnelAddress,\r
- CpuMpData->AddressMap.RendezvousFunnelSize\r
+ CpuMpData->AddressMap.RendezvousFunnelSize +\r
+ CpuMpData->AddressMap.SwitchToRealSize\r
);\r
}\r
\r
);\r
}\r
\r
+/**\r
+ Calculate the size of the reset stack.\r
+\r
+ @return Total amount of memory required for stacks\r
+**/\r
+STATIC\r
+UINTN\r
+GetApResetStackSize (\r
+ VOID\r
+ )\r
+{\r
+ return AP_RESET_STACK_SIZE * PcdGet32(PcdCpuMaxLogicalProcessorNumber);\r
+}\r
+\r
+/**\r
+ Calculate the size of the reset vector.\r
+\r
+ @param[in] AddressMap The pointer to Address Map structure.\r
+\r
+ @return Total amount of memory required for the AP reset area\r
+**/\r
+STATIC\r
+UINTN\r
+GetApResetVectorSize (\r
+ IN MP_ASSEMBLY_ADDRESS_MAP *AddressMap\r
+ )\r
+{\r
+ UINTN Size;\r
+\r
+ Size = ALIGN_VALUE (AddressMap->RendezvousFunnelSize +\r
+ AddressMap->SwitchToRealSize +\r
+ sizeof (MP_CPU_EXCHANGE_INFO),\r
+ CPU_STACK_ALIGNMENT);\r
+ Size += GetApResetStackSize ();\r
+\r
+ return Size;\r
+}\r
+\r
/**\r
Allocate reset vector buffer.\r
\r
UINTN ApResetVectorSize;\r
\r
if (CpuMpData->WakeupBuffer == (UINTN) -1) {\r
- ApResetVectorSize = CpuMpData->AddressMap.RendezvousFunnelSize +\r
- sizeof (MP_CPU_EXCHANGE_INFO);\r
+ ApResetVectorSize = GetApResetVectorSize (&CpuMpData->AddressMap);\r
\r
CpuMpData->WakeupBuffer = GetWakeupBuffer (ApResetVectorSize);\r
CpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN)\r
- (CpuMpData->WakeupBuffer + CpuMpData->AddressMap.RendezvousFunnelSize);\r
+ (CpuMpData->WakeupBuffer +\r
+ CpuMpData->AddressMap.RendezvousFunnelSize +\r
+ CpuMpData->AddressMap.SwitchToRealSize);\r
CpuMpData->WakeupBufferHigh = GetModeTransitionBuffer (\r
- CpuMpData->AddressMap.RendezvousFunnelSize -\r
+ CpuMpData->AddressMap.RendezvousFunnelSize +\r
+ CpuMpData->AddressMap.SwitchToRealSize -\r
CpuMpData->AddressMap.ModeTransitionOffset\r
);\r
+ //\r
+ // The reset stack starts at the end of the buffer.\r
+ //\r
+ CpuMpData->SevEsAPResetStackStart = CpuMpData->WakeupBuffer + ApResetVectorSize;\r
}\r
BackupAndPrepareWakeupBuffer (CpuMpData);\r
}\r
IN CPU_MP_DATA *CpuMpData\r
)\r
{\r
- RestoreWakeupBuffer (CpuMpData);\r
+ //\r
+ // If SEV-ES is enabled, the reset area is needed for AP parking and\r
+ // and AP startup in the OS, so the reset area is reserved. Do not\r
+ // perform the restore as this will overwrite memory which has data\r
+ // needed by SEV-ES.\r
+ //\r
+ if (!CpuMpData->SevEsIsEnabled) {\r
+ RestoreWakeupBuffer (CpuMpData);\r
+ }\r
+}\r
+\r
+/**\r
+ Allocate the SEV-ES AP jump table buffer.\r
+\r
+ @param[in, out] CpuMpData The pointer to CPU MP Data structure.\r
+**/\r
+VOID\r
+AllocateSevEsAPMemory (\r
+ IN OUT CPU_MP_DATA *CpuMpData\r
+ )\r
+{\r
+ if (CpuMpData->SevEsAPBuffer == (UINTN) -1) {\r
+ CpuMpData->SevEsAPBuffer =\r
+ CpuMpData->SevEsIsEnabled ? GetSevEsAPMemory () : 0;\r
+ }\r
+}\r
+\r
+/**\r
+ Program the SEV-ES AP jump table buffer.\r
+\r
+ @param[in] SipiVector The SIPI vector used for the AP Reset\r
+**/\r
+VOID\r
+SetSevEsJumpTable (\r
+ IN UINTN SipiVector\r
+ )\r
+{\r
+ SEV_ES_AP_JMP_FAR *JmpFar;\r
+ UINT32 Offset, InsnByte;\r
+ UINT8 LoNib, HiNib;\r
+\r
+ JmpFar = (SEV_ES_AP_JMP_FAR *) FixedPcdGet32 (PcdSevEsWorkAreaBase);\r
+ ASSERT (JmpFar != NULL);\r
+\r
+ //\r
+ // Obtain the address of the Segment/Rip location in the workarea.\r
+ // This will be set to a value derived from the SIPI vector and will\r
+ // be the memory address used for the far jump below.\r
+ //\r
+ Offset = FixedPcdGet32 (PcdSevEsWorkAreaBase);\r
+ Offset += sizeof (JmpFar->InsnBuffer);\r
+ LoNib = (UINT8) Offset;\r
+ HiNib = (UINT8) (Offset >> 8);\r
+\r
+ //\r
+ // Program the workarea (which is the initial AP boot address) with\r
+ // far jump to the SIPI vector (where XX and YY represent the\r
+ // address of where the SIPI vector is stored.\r
+ //\r
+ // JMP FAR [CS:XXYY] => 2E FF 2E YY XX\r
+ //\r
+ InsnByte = 0;\r
+ JmpFar->InsnBuffer[InsnByte++] = 0x2E; // CS override prefix\r
+ JmpFar->InsnBuffer[InsnByte++] = 0xFF; // JMP (FAR)\r
+ JmpFar->InsnBuffer[InsnByte++] = 0x2E; // ModRM (JMP memory location)\r
+ JmpFar->InsnBuffer[InsnByte++] = LoNib; // YY offset ...\r
+ JmpFar->InsnBuffer[InsnByte++] = HiNib; // XX offset ...\r
+\r
+ //\r
+ // Program the Segment/Rip based on the SIPI vector (always at least\r
+ // 16-byte aligned, so Rip is set to 0).\r
+ //\r
+ JmpFar->Rip = 0;\r
+ JmpFar->Segment = (UINT16) (SipiVector >> 4);\r
}\r
\r
/**\r
CpuMpData->InitFlag != ApInitDone) {\r
ResetVectorRequired = TRUE;\r
AllocateResetVector (CpuMpData);\r
+ AllocateSevEsAPMemory (CpuMpData);\r
FillExchangeInfoData (CpuMpData);\r
SaveLocalApicTimerSetting (CpuMpData);\r
}\r
}\r
}\r
if (ResetVectorRequired) {\r
+ //\r
+ // For SEV-ES, the initial AP boot address will be defined by\r
+ // PcdSevEsWorkAreaBase. The Segment/Rip must be the jump address\r
+ // from the original INIT-SIPI-SIPI.\r
+ //\r
+ if (CpuMpData->SevEsIsEnabled) {\r
+ SetSevEsJumpTable (ExchangeInfo->BufferStart);\r
+ }\r
+\r
//\r
// Wakeup all APs\r
//\r
SendInitSipiSipiAllExcludingSelf ((UINT32) ExchangeInfo->BufferStart);\r
}\r
if (CpuMpData->InitFlag == ApInitConfig) {\r
- //\r
- // The AP enumeration algorithm below is suitable for two use cases.\r
- //\r
- // (1) The check-in time for an individual AP is bounded, and APs run\r
- // through their initialization routines strongly concurrently. In\r
- // particular, the number of concurrently running APs\r
- // ("NumApsExecuting") is never expected to fall to zero\r
- // *temporarily* -- it is expected to fall to zero only when all\r
- // APs have checked-in.\r
- //\r
- // In this case, the platform is supposed to set\r
- // PcdCpuApInitTimeOutInMicroSeconds to a low-ish value (just long\r
- // enough for one AP to start initialization). The timeout will be\r
- // reached soon, and remaining APs are collected by watching\r
- // NumApsExecuting fall to zero. If NumApsExecuting falls to zero\r
- // mid-process, while some APs have not completed initialization,\r
- // the behavior is undefined.\r
- //\r
- // (2) The check-in time for an individual AP is unbounded, and/or APs\r
- // may complete their initializations widely spread out. In\r
- // particular, some APs may finish initialization before some APs\r
- // even start.\r
- //\r
- // In this case, the platform is supposed to set\r
- // PcdCpuApInitTimeOutInMicroSeconds to a high-ish value. The AP\r
- // enumeration will always take that long (except when the boot CPU\r
- // count happens to be maximal, that is,\r
- // PcdCpuMaxLogicalProcessorNumber). All APs are expected to\r
- // check-in before the timeout, and NumApsExecuting is assumed zero\r
- // at timeout. APs that miss the time-out may cause undefined\r
- // behavior.\r
- //\r
- TimedWaitForApFinish (\r
- CpuMpData,\r
- PcdGet32 (PcdCpuMaxLogicalProcessorNumber) - 1,\r
- PcdGet32 (PcdCpuApInitTimeOutInMicroSeconds)\r
- );\r
+ if (PcdGet32 (PcdCpuBootLogicalProcessorNumber) > 0) {\r
+ //\r
+ // The AP enumeration algorithm below is suitable only when the\r
+ // platform can tell us the *exact* boot CPU count in advance.\r
+ //\r
+ // The wait below finishes only when the detected AP count reaches\r
+ // (PcdCpuBootLogicalProcessorNumber - 1), regardless of how long that\r
+ // takes. If at least one AP fails to check in (meaning a platform\r
+ // hardware bug), the detection hangs forever, by design. If the actual\r
+ // boot CPU count in the system is higher than\r
+ // PcdCpuBootLogicalProcessorNumber (meaning a platform\r
+ // misconfiguration), then some APs may complete initialization after\r
+ // the wait finishes, and cause undefined behavior.\r
+ //\r
+ TimedWaitForApFinish (\r
+ CpuMpData,\r
+ PcdGet32 (PcdCpuBootLogicalProcessorNumber) - 1,\r
+ MAX_UINT32 // approx. 71 minutes\r
+ );\r
+ } else {\r
+ //\r
+ // The AP enumeration algorithm below is suitable for two use cases.\r
+ //\r
+ // (1) The check-in time for an individual AP is bounded, and APs run\r
+ // through their initialization routines strongly concurrently. In\r
+ // particular, the number of concurrently running APs\r
+ // ("NumApsExecuting") is never expected to fall to zero\r
+ // *temporarily* -- it is expected to fall to zero only when all\r
+ // APs have checked-in.\r
+ //\r
+ // In this case, the platform is supposed to set\r
+ // PcdCpuApInitTimeOutInMicroSeconds to a low-ish value (just long\r
+ // enough for one AP to start initialization). The timeout will be\r
+ // reached soon, and remaining APs are collected by watching\r
+ // NumApsExecuting fall to zero. If NumApsExecuting falls to zero\r
+ // mid-process, while some APs have not completed initialization,\r
+ // the behavior is undefined.\r
+ //\r
+ // (2) The check-in time for an individual AP is unbounded, and/or APs\r
+ // may complete their initializations widely spread out. In\r
+ // particular, some APs may finish initialization before some APs\r
+ // even start.\r
+ //\r
+ // In this case, the platform is supposed to set\r
+ // PcdCpuApInitTimeOutInMicroSeconds to a high-ish value. The AP\r
+ // enumeration will always take that long (except when the boot CPU\r
+ // count happens to be maximal, that is,\r
+ // PcdCpuMaxLogicalProcessorNumber). All APs are expected to\r
+ // check-in before the timeout, and NumApsExecuting is assumed zero\r
+ // at timeout. APs that miss the time-out may cause undefined\r
+ // behavior.\r
+ //\r
+ TimedWaitForApFinish (\r
+ CpuMpData,\r
+ PcdGet32 (PcdCpuMaxLogicalProcessorNumber) - 1,\r
+ PcdGet32 (PcdCpuApInitTimeOutInMicroSeconds)\r
+ );\r
\r
- while (CpuMpData->MpCpuExchangeInfo->NumApsExecuting != 0) {\r
- CpuPause();\r
+ while (CpuMpData->MpCpuExchangeInfo->NumApsExecuting != 0) {\r
+ CpuPause();\r
+ }\r
}\r
} else {\r
//\r
*(UINT32 *) CpuData->StartupApSignal = WAKEUP_AP_SIGNAL;\r
if (ResetVectorRequired) {\r
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
+\r
+ //\r
+ // For SEV-ES, the initial AP boot address will be defined by\r
+ // PcdSevEsWorkAreaBase. The Segment/Rip must be the jump address\r
+ // from the original INIT-SIPI-SIPI.\r
+ //\r
+ if (CpuMpData->SevEsIsEnabled) {\r
+ SetSevEsJumpTable (ExchangeInfo->BufferStart);\r
+ }\r
+\r
SendInitSipiSipi (\r
CpuInfoInHob[ProcessorNumber].ApicId,\r
(UINT32) ExchangeInfo->BufferStart\r
UINTN ApResetVectorSize;\r
UINTN BackupBufferAddr;\r
UINTN ApIdtBase;\r
- VOID *MicrocodePatchInRam;\r
\r
OldCpuMpData = GetCpuMpDataFromGuidedHob ();\r
if (OldCpuMpData == NULL) {\r
ASSERT (MaxLogicalProcessorNumber != 0);\r
\r
AsmGetAddressMap (&AddressMap);\r
- ApResetVectorSize = AddressMap.RendezvousFunnelSize + sizeof (MP_CPU_EXCHANGE_INFO);\r
+ ApResetVectorSize = GetApResetVectorSize (&AddressMap);\r
ApStackSize = PcdGet32(PcdCpuApStackSize);\r
ApLoopMode = GetApLoopMode (&MonitorFilterSize);\r
\r
CpuMpData->SwitchBspFlag = FALSE;\r
CpuMpData->CpuData = (CPU_AP_DATA *) (CpuMpData + 1);\r
CpuMpData->CpuInfoInHob = (UINT64) (UINTN) (CpuMpData->CpuData + MaxLogicalProcessorNumber);\r
- if (OldCpuMpData == NULL) {\r
- CpuMpData->MicrocodePatchRegionSize = PcdGet64 (PcdCpuMicrocodePatchRegionSize);\r
- //\r
- // If platform has more than one CPU, relocate microcode to memory to reduce\r
- // loading microcode time.\r
- //\r
- MicrocodePatchInRam = NULL;\r
- if (MaxLogicalProcessorNumber > 1) {\r
- MicrocodePatchInRam = AllocatePages (\r
- EFI_SIZE_TO_PAGES (\r
- (UINTN)CpuMpData->MicrocodePatchRegionSize\r
- )\r
- );\r
- }\r
- if (MicrocodePatchInRam == NULL) {\r
- //\r
- // there is only one processor, or no microcode patch is available, or\r
- // memory allocation failed\r
- //\r
- CpuMpData->MicrocodePatchAddress = PcdGet64 (PcdCpuMicrocodePatchAddress);\r
- } else {\r
- //\r
- // there are multiple processors, and a microcode patch is available, and\r
- // memory allocation succeeded\r
- //\r
- CopyMem (\r
- MicrocodePatchInRam,\r
- (VOID *)(UINTN)PcdGet64 (PcdCpuMicrocodePatchAddress),\r
- (UINTN)CpuMpData->MicrocodePatchRegionSize\r
- );\r
- CpuMpData->MicrocodePatchAddress = (UINTN)MicrocodePatchInRam;\r
- }\r
- }else {\r
- CpuMpData->MicrocodePatchRegionSize = OldCpuMpData->MicrocodePatchRegionSize;\r
- CpuMpData->MicrocodePatchAddress = OldCpuMpData->MicrocodePatchAddress;\r
- }\r
InitializeSpinLock(&CpuMpData->MpLock);\r
+ CpuMpData->SevEsIsEnabled = PcdGetBool (PcdSevEsIsEnabled);\r
+ CpuMpData->SevEsAPBuffer = (UINTN) -1;\r
+ CpuMpData->GhcbBase = PcdGet64 (PcdGhcbBase);\r
\r
//\r
// Make sure no memory usage outside of the allocated buffer.\r
(UINT32 *)(MonitorBuffer + MonitorFilterSize * Index);\r
}\r
//\r
- // Load Microcode on BSP\r
- //\r
- MicrocodeDetect (CpuMpData, TRUE);\r
- //\r
- // Store BSP's MTRR setting\r
- //\r
- MtrrGetAllMtrrs (&CpuMpData->MtrrTable);\r
- //\r
// Enable the local APIC for Virtual Wire Mode.\r
//\r
ProgramVirtualWireMode ();\r
// APs have been wakeup before, just get the CPU Information\r
// from HOB\r
//\r
+ OldCpuMpData->NewCpuMpData = CpuMpData;\r
CpuMpData->CpuCount = OldCpuMpData->CpuCount;\r
CpuMpData->BspNumber = OldCpuMpData->BspNumber;\r
- CpuMpData->InitFlag = ApInitReconfig;\r
CpuMpData->CpuInfoInHob = OldCpuMpData->CpuInfoInHob;\r
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
for (Index = 0; Index < CpuMpData->CpuCount; Index++) {\r
InitializeSpinLock(&CpuMpData->CpuData[Index].ApLock);\r
- if (CpuInfoInHob[Index].InitialApicId >= 255 || Index > 254) {\r
- CpuMpData->X2ApicEnable = TRUE;\r
- }\r
CpuMpData->CpuData[Index].CpuHealthy = (CpuInfoInHob[Index].Health == 0)? TRUE:FALSE;\r
CpuMpData->CpuData[Index].ApFunction = 0;\r
- CopyMem (&CpuMpData->CpuData[Index].VolatileRegisters, &VolatileRegisters, sizeof (CPU_VOLATILE_REGISTERS));\r
}\r
- if (MaxLogicalProcessorNumber > 1) {\r
- //\r
- // Wakeup APs to do some AP initialize sync\r
- //\r
- WakeUpAP (CpuMpData, TRUE, 0, ApInitializeSync, CpuMpData, TRUE);\r
+ }\r
+\r
+ if (!GetMicrocodePatchInfoFromHob (\r
+ &CpuMpData->MicrocodePatchAddress,\r
+ &CpuMpData->MicrocodePatchRegionSize\r
+ )) {\r
+ //\r
+ // The microcode patch information cache HOB does not exist, which means\r
+ // the microcode patches data has not been loaded into memory yet\r
+ //\r
+ ShadowMicrocodeUpdatePatch (CpuMpData);\r
+ }\r
+\r
+ //\r
+ // Detect and apply Microcode on BSP\r
+ //\r
+ MicrocodeDetect (CpuMpData, CpuMpData->BspNumber);\r
+ //\r
+ // Store BSP's MTRR setting\r
+ //\r
+ MtrrGetAllMtrrs (&CpuMpData->MtrrTable);\r
+\r
+ //\r
+ // Wakeup APs to do some AP initialize sync (Microcode & MTRR)\r
+ //\r
+ if (CpuMpData->CpuCount > 1) {\r
+ if (OldCpuMpData != NULL) {\r
//\r
- // Wait for all APs finished initialization\r
+ // Only needs to use this flag for DXE phase to update the wake up\r
+ // buffer. Wakeup buffer allocated in PEI phase is no longer valid\r
+ // in DXE.\r
//\r
- while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) {\r
- CpuPause ();\r
- }\r
+ CpuMpData->InitFlag = ApInitReconfig;\r
+ }\r
+ WakeUpAP (CpuMpData, TRUE, 0, ApInitializeSync, CpuMpData, TRUE);\r
+ //\r
+ // Wait for all APs finished initialization\r
+ //\r
+ while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) {\r
+ CpuPause ();\r
+ }\r
+ if (OldCpuMpData != NULL) {\r
CpuMpData->InitFlag = ApInitDone;\r
- for (Index = 0; Index < CpuMpData->CpuCount; Index++) {\r
- SetApState (&CpuMpData->CpuData[Index], CpuStateIdle);\r
- }\r
+ }\r
+ for (Index = 0; Index < CpuMpData->CpuCount; Index++) {\r
+ SetApState (&CpuMpData->CpuData[Index], CpuStateIdle);\r
}\r
}\r
\r
CPU_MP_DATA *CpuMpData;\r
UINTN CallerNumber;\r
CPU_INFO_IN_HOB *CpuInfoInHob;\r
+ UINTN OriginalProcessorNumber;\r
\r
CpuMpData = GetCpuMpData ();\r
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
\r
+ //\r
+ // Lower 24 bits contains the actual processor number.\r
+ //\r
+ OriginalProcessorNumber = ProcessorNumber;\r
+ ProcessorNumber &= BIT24 - 1;\r
+\r
//\r
// Check whether caller processor is BSP\r
//\r
&ProcessorInfoBuffer->Location.Thread\r
);\r
\r
+ if ((OriginalProcessorNumber & CPU_V2_EXTENDED_TOPOLOGY) != 0) {\r
+ GetProcessorLocation2ByApicId (\r
+ CpuInfoInHob[ProcessorNumber].ApicId,\r
+ &ProcessorInfoBuffer->ExtendedInformation.Location2.Package,\r
+ &ProcessorInfoBuffer->ExtendedInformation.Location2.Die,\r
+ &ProcessorInfoBuffer->ExtendedInformation.Location2.Tile,\r
+ &ProcessorInfoBuffer->ExtendedInformation.Location2.Module,\r
+ &ProcessorInfoBuffer->ExtendedInformation.Location2.Core,\r
+ &ProcessorInfoBuffer->ExtendedInformation.Location2.Thread\r
+ );\r
+ }\r
+\r
if (HealthData != NULL) {\r
HealthData->Uint32 = CpuInfoInHob[ProcessorNumber].Health;\r
}\r
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