/** @file\r
Page table manipulation functions for IA-32 processors\r
\r
-Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
#include "PiSmmCpuDxeSmm.h"\r
\r
+/**\r
+ Disable CET.\r
+**/\r
+VOID\r
+EFIAPI\r
+DisableCet (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Enable CET.\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableCet (\r
+ VOID\r
+ );\r
+\r
/**\r
Create PageTable for SMM use.\r
\r
//\r
InitializeSpinLock (mPFLock);\r
\r
- if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {\r
+ mPhysicalAddressBits = 32;\r
+\r
+ if (FeaturePcdGet (PcdCpuSmmProfileEnable) ||\r
+ HEAP_GUARD_NONSTOP_MODE ||\r
+ NULL_DETECTION_NONSTOP_MODE) {\r
//\r
// Set own Page Fault entry instead of the default one, because SMM Profile\r
// feature depends on IRET instruction to do Single Step\r
VOID\r
EFIAPI\r
SmiPFHandler (\r
- IN EFI_EXCEPTION_TYPE InterruptType,\r
- IN EFI_SYSTEM_CONTEXT SystemContext\r
+ IN EFI_EXCEPTION_TYPE InterruptType,\r
+ IN EFI_SYSTEM_CONTEXT SystemContext\r
)\r
{\r
UINTN PFAddress;\r
//\r
if ((PFAddress >= mCpuHotPlugData.SmrrBase) &&\r
(PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) {\r
+ DumpCpuContext (InterruptType, SystemContext);\r
CpuIndex = GetCpuIndex ();\r
GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * mSmmStackSize);\r
if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&\r
(PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) {\r
DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n"));\r
} else {\r
- DEBUG ((DEBUG_ERROR, "SMM exception data - 0x%x(", SystemContext.SystemContextIa32->ExceptionData));\r
- DEBUG ((DEBUG_ERROR, "I:%x, R:%x, U:%x, W:%x, P:%x",\r
- (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0,\r
- (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_RSVD) != 0,\r
- (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_US) != 0,\r
- (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_WR) != 0,\r
- (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_P) != 0\r
- ));\r
- DEBUG ((DEBUG_ERROR, ")\n"));\r
if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {\r
DEBUG ((DEBUG_ERROR, "SMM exception at execution (0x%x)\n", PFAddress));\r
DEBUG_CODE (\r
DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);\r
);\r
}\r
+\r
+ if (HEAP_GUARD_NONSTOP_MODE) {\r
+ GuardPagePFHandler (SystemContext.SystemContextIa32->ExceptionData);\r
+ goto Exit;\r
+ }\r
}\r
CpuDeadLoop ();\r
+ goto Exit;\r
}\r
\r
//\r
- // If a page fault occurs in SMM range\r
+ // If a page fault occurs in non-SMRAM range.\r
//\r
if ((PFAddress < mCpuHotPlugData.SmrrBase) ||\r
(PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {\r
if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {\r
+ DumpCpuContext (InterruptType, SystemContext);\r
DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%x) out of SMM range after SMM is locked!\n", PFAddress));\r
DEBUG_CODE (\r
DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextIa32->Esp);\r
);\r
CpuDeadLoop ();\r
+ goto Exit;\r
+ }\r
+\r
+ //\r
+ // If NULL pointer was just accessed\r
+ //\r
+ if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0 &&\r
+ (PFAddress < EFI_PAGE_SIZE)) {\r
+ DumpCpuContext (InterruptType, SystemContext);\r
+ DEBUG ((DEBUG_ERROR, "!!! NULL pointer access !!!\n"));\r
+ DEBUG_CODE (\r
+ DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);\r
+ );\r
+\r
+ if (NULL_DETECTION_NONSTOP_MODE) {\r
+ GuardPagePFHandler (SystemContext.SystemContextIa32->ExceptionData);\r
+ goto Exit;\r
+ }\r
+\r
+ CpuDeadLoop ();\r
+ goto Exit;\r
+ }\r
+\r
+ if (IsSmmCommBufferForbiddenAddress (PFAddress)) {\r
+ DumpCpuContext (InterruptType, SystemContext);\r
+ DEBUG ((DEBUG_ERROR, "Access SMM communication forbidden address (0x%x)!\n", PFAddress));\r
+ DEBUG_CODE (\r
+ DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);\r
+ );\r
+ CpuDeadLoop ();\r
+ goto Exit;\r
}\r
}\r
\r
SystemContext.SystemContextIa32->ExceptionData\r
);\r
} else {\r
+ DumpCpuContext (InterruptType, SystemContext);\r
SmiDefaultPFHandler ();\r
}\r
\r
+Exit:\r
ReleaseSpinLock (mPFLock);\r
}\r
\r
UINT64 *L3PageTable;\r
BOOLEAN IsSplitted;\r
BOOLEAN PageTableSplitted;\r
+ BOOLEAN CetEnabled;\r
+\r
+ //\r
+ // Don't mark page table to read-only if heap guard is enabled.\r
+ //\r
+ // BIT2: SMM page guard enabled\r
+ // BIT3: SMM pool guard enabled\r
+ //\r
+ if ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) {\r
+ DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as heap guard is enabled\n"));\r
+ return ;\r
+ }\r
+\r
+ //\r
+ // Don't mark page table to read-only if SMM profile is enabled.\r
+ //\r
+ if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {\r
+ DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as SMM profile is enabled\n"));\r
+ return ;\r
+ }\r
\r
DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n"));\r
\r
// Disable write protection, because we need mark page table to be write protected.\r
// We need *write* page table memory, to mark itself to be *read only*.\r
//\r
+ CetEnabled = ((AsmReadCr4() & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;\r
+ if (CetEnabled) {\r
+ //\r
+ // CET must be disabled if WP is disabled.\r
+ //\r
+ DisableCet();\r
+ }\r
AsmWriteCr0 (AsmReadCr0() & ~CR0_WP);\r
\r
do {\r
PageTableSplitted = (PageTableSplitted || IsSplitted);\r
\r
for (Index3 = 0; Index3 < 4; Index3++) {\r
- L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & PAGING_4K_ADDRESS_MASK_64);\r
+ L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);\r
if (L2PageTable == NULL) {\r
continue;\r
}\r
// 2M\r
continue;\r
}\r
- L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & PAGING_4K_ADDRESS_MASK_64);\r
+ L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);\r
if (L1PageTable == NULL) {\r
continue;\r
}\r
// Enable write protection, after page table updated.\r
//\r
AsmWriteCr0 (AsmReadCr0() | CR0_WP);\r
+ if (CetEnabled) {\r
+ //\r
+ // re-enable CET.\r
+ //\r
+ EnableCet();\r
+ }\r
\r
return ;\r
}\r
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