/** @file\r
SMM MP service implementation\r
\r
-Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
// Sync with APs 1st timeout\r
//\r
for (Timer = StartSyncTimer ();\r
- !IsSyncTimerTimeout (Timer) && !(LmceEn && LmceSignal) &&\r
- !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED);\r
+ !IsSyncTimerTimeout (Timer) && !(LmceEn && LmceSignal);\r
)\r
{\r
+ mSmmMpSyncData->AllApArrivedWithException = AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED);\r
+ if (mSmmMpSyncData->AllApArrivedWithException) {\r
+ break;\r
+ }\r
+\r
CpuPause ();\r
}\r
\r
// Sync with APs 2nd timeout.\r
//\r
for (Timer = StartSyncTimer ();\r
- !IsSyncTimerTimeout (Timer) &&\r
- !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED);\r
+ !IsSyncTimerTimeout (Timer);\r
)\r
{\r
+ mSmmMpSyncData->AllApArrivedWithException = AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED);\r
+ if (mSmmMpSyncData->AllApArrivedWithException) {\r
+ break;\r
+ }\r
+\r
CpuPause ();\r
}\r
}\r
*mSmmMpSyncData->InsideSmm = FALSE;\r
*mSmmMpSyncData->AllCpusInSync = FALSE;\r
\r
+ mSmmMpSyncData->AllApArrivedWithException = FALSE;\r
+\r
for (CpuIndex = 0; CpuIndex < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; CpuIndex++) {\r
mSmmMpSyncData->CpuData[CpuIndex].Busy =\r
(SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Busy + mSemaphoreSize * CpuIndex);\r