UefiCpuPkg/PiSmmCpuDxeSmm: Update to consume SpeculationBarrier

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
old mode 100755 (executable)
new mode 100644 (file)
index c5b67e3..8c9fa14
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -125,6 +125,12 @@ UINTN                    mSmmCpuSmramRangeCount;
 \r
 UINT8                    mPhysicalAddressBits;\r
 \r
+//\r
+// Control register contents saved for SMM S3 resume state initialization.\r
+//\r
+UINT32                   mSmmCr0;\r
+UINT32                   mSmmCr4;\r
+\r
 /**\r
   Initialize IDT to setup exception handlers for SMM.\r
 \r
@@ -231,6 +237,11 @@ SmmReadSaveState (
   if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
+  //\r
+  // The SpeculationBarrier() call here is to ensure the above check for the\r
+  // CpuIndex has been completed before the execution of subsequent codes.\r
+  //\r
+  SpeculationBarrier ();\r
 \r
   //\r
   // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID\r
@@ -405,9 +416,11 @@ SmmRelocateBases (
   //\r
   // Patch ASM code template with current CR0, CR3, and CR4 values\r
   //\r
-  gSmmCr0 = (UINT32)AsmReadCr0 ();\r
+  mSmmCr0 = (UINT32)AsmReadCr0 ();\r
+  PatchInstructionX86 (gPatchSmmCr0, mSmmCr0, 4);\r
   PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);\r
-  gSmmCr4 = (UINT32)AsmReadCr4 ();\r
+  mSmmCr4 = (UINT32)AsmReadCr4 ();\r
+  PatchInstructionX86 (gPatchSmmCr4, mSmmCr4, 4);\r
 \r
   //\r
   // Patch GDTR for SMM base relocation\r
@@ -561,13 +574,6 @@ PiCpuSmmEntry (
     EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_INIT\r
     );\r
 \r
-  //\r
-  // Fix segment address of the long-mode-switch jump\r
-  //\r
-  if (sizeof (UINTN) == sizeof (UINT64)) {\r
-    gSmmJmpAddr.Segment = LONG_MODE_CODE_SEGMENT;\r
-  }\r
-\r
   //\r
   // Find out SMRR Base and SMRR Size\r
   //\r
@@ -847,7 +853,11 @@ PiCpuSmmEntry (
   //\r
   // Set SMI stack for SMM base relocation\r
   //\r
-  gSmmInitStack = (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN));\r
+  PatchInstructionX86 (\r
+    gPatchSmmInitStack,\r
+    (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN)),\r
+    sizeof (UINTN)\r
+    );\r
 \r
   //\r
   // Initialize IDT\r