extern CPU_HOT_PLUG_DATA mCpuHotPlugData;\r
extern UINTN mMaxNumberOfCpus;\r
extern UINTN mNumberOfCpus;\r
-extern BOOLEAN mRestoreSmmConfigurationInS3;\r
extern EFI_SMM_CPU_PROTOCOL mSmmCpu;\r
\r
///\r
/// The type of SMM CPU Information\r
///\r
typedef struct {\r
- SPIN_LOCK Busy;\r
+ SPIN_LOCK *Busy;\r
volatile EFI_AP_PROCEDURE Procedure;\r
volatile VOID *Parameter;\r
- volatile UINT32 Run;\r
- volatile BOOLEAN Present;\r
+ volatile UINT32 *Run;\r
+ volatile BOOLEAN *Present;\r
} SMM_CPU_DATA_BLOCK;\r
\r
typedef enum {\r
// so that UC cache-ability can be set together.\r
//\r
SMM_CPU_DATA_BLOCK *CpuData;\r
- volatile UINT32 Counter;\r
+ volatile UINT32 *Counter;\r
volatile UINT32 BspIndex;\r
- volatile BOOLEAN InsideSmm;\r
- volatile BOOLEAN AllCpusInSync;\r
+ volatile BOOLEAN *InsideSmm;\r
+ volatile BOOLEAN *AllCpusInSync;\r
volatile SMM_CPU_SYNC_MODE EffectiveSyncMode;\r
volatile BOOLEAN SwitchBsp;\r
volatile BOOLEAN *CandidateBsp;\r
} SMM_DISPATCHER_MP_SYNC_DATA;\r
\r
+#define MSR_SPIN_LOCK_INIT_NUM 15\r
+\r
typedef struct {\r
- SPIN_LOCK SpinLock;\r
+ SPIN_LOCK *SpinLock;\r
UINT32 MsrIndex;\r
} MP_MSR_LOCK;\r
\r
volatile BOOLEAN *AllCpusInSync;\r
SPIN_LOCK *PFLock;\r
SPIN_LOCK *CodeAccessCheckLock;\r
+ SPIN_LOCK *MemoryMappedLock;\r
} SMM_CPU_SEMAPHORE_GLOBAL;\r
\r
+///\r
+/// All semaphores for each processor\r
+///\r
+typedef struct {\r
+ SPIN_LOCK *Busy;\r
+ volatile UINT32 *Run;\r
+ volatile BOOLEAN *Present;\r
+} SMM_CPU_SEMAPHORE_CPU;\r
+\r
+///\r
+/// All MSRs semaphores' pointer and counter\r
+///\r
+typedef struct {\r
+ SPIN_LOCK *Msr;\r
+ UINTN AvailableCounter;\r
+} SMM_CPU_SEMAPHORE_MSR;\r
+\r
///\r
/// All semaphores' information\r
///\r
typedef struct {\r
SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal;\r
+ SMM_CPU_SEMAPHORE_CPU SemaphoreCpu;\r
+ SMM_CPU_SEMAPHORE_MSR SemaphoreMsr;\r
} SMM_CPU_SEMAPHORES;\r
\r
extern IA32_DESCRIPTOR gcSmiGdtr;\r
extern VOID *gcSmiIdtrPtr;\r
extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;\r
extern UINT64 gPhyMask;\r
-extern ACPI_CPU_DATA mAcpiCpuData;\r
extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;\r
-extern VOID *mGdtForAp;\r
-extern VOID *mIdtForAp;\r
-extern VOID *mMachineCheckHandlerForAp;\r
extern UINTN mSmmStackArrayBase;\r
extern UINTN mSmmStackArrayEnd;\r
extern UINTN mSmmStackSize;\r
extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;\r
extern IA32_DESCRIPTOR gcSmiInitGdtr;\r
+extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores;\r
+extern UINTN mSemaphoreSize;\r
+extern SPIN_LOCK *mPFLock;\r
+extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;\r
+extern SPIN_LOCK *mMemoryMappedLock;\r
\r
/**\r
Create 4G PageTable in SMRAM.\r
);\r
\r
/**\r
- The function is invoked before SMBASE relocation in S3 path to restores CPU status.\r
-\r
- The function is invoked before SMBASE relocation in S3 path. It does first time microcode load\r
- and restores MTRRs for both BSP and APs.\r
-\r
-**/\r
-VOID\r
-EarlyInitializeCpu (\r
- VOID\r
- );\r
-\r
-/**\r
- The function is invoked after SMBASE relocation in S3 path to restores CPU status.\r
+ Relocate SmmBases for each processor.\r
\r
- The function is invoked after SMBASE relocation in S3 path. It restores configuration according to\r
- data saved by normal boot path for both BSP and APs.\r
+ Execute on first boot and all S3 resumes\r
\r
**/\r
VOID\r
-InitializeCpu (\r
+EFIAPI\r
+SmmRelocateBases (\r
VOID\r
);\r
\r
IN UINTN Pages\r
);\r
\r
+\r
+//\r
+// S3 related global variable and function prototype.\r
+//\r
+\r
+extern BOOLEAN mSmmS3Flag;\r
+\r
+/**\r
+ Initialize SMM S3 resume state structure used during S3 Resume.\r
+\r
+ @param[in] Cr3 The base address of the page tables to use in SMM.\r
+\r
+**/\r
+VOID\r
+InitSmmS3ResumeState (\r
+ IN UINT32 Cr3\r
+ );\r
+\r
+/**\r
+ Get ACPI CPU data.\r
+\r
+**/\r
+VOID\r
+GetAcpiCpuData (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Restore SMM Configuration in S3 boot path.\r
+\r
+**/\r
+VOID\r
+RestoreSmmConfigurationInS3 (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Get ACPI S3 enable flag.\r
+\r
+**/\r
+VOID\r
+GetAcpiS3EnableFlag (\r
+ VOID\r
+ );\r
+\r
#endif\r