UefiCpuPkg/PiSmmCpuDxeSmm: Update saved SMM ranges check in SmmProfile

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.h

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index 69c54fbee6e91afba0e7685be6be80fd23e19bab..fc9b06e972ae1bcd9111eadef4c6b6930c8bf15b 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -1,7 +1,9 @@
 /** @file\r
 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
 \r
-Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -103,6 +105,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
 #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
 \r
+#define SMRR_MAX_ADDRESS       BASE_4GB\r
+\r
 typedef enum {\r
   PageNone,\r
   Page4K,\r
@@ -184,7 +188,6 @@ extern EFI_SMM_CPU_PROTOCOL   mSmmCpu;
 ///\r
 extern UINT8  mSmmSaveStateRegisterLma;\r
 \r
-\r
 //\r
 // SMM CPU Protocol function prototypes.\r
 //\r
@@ -414,6 +417,13 @@ extern UINTN                               mSemaphoreSize;
 extern SPIN_LOCK                           *mPFLock;\r
 extern SPIN_LOCK                           *mConfigSmmCodeAccessCheckLock;\r
 extern SPIN_LOCK                           *mMemoryMappedLock;\r
+extern EFI_SMRAM_DESCRIPTOR                *mSmmCpuSmramRanges;\r
+extern UINTN                               mSmmCpuSmramRangeCount;\r
+\r
+//\r
+// Copy of the PcdPteMemoryEncryptionAddressOrMask\r
+//\r
+extern UINT64  mAddressEncMask;\r
 \r
 /**\r
   Create 4G PageTable in SMRAM.\r