UefiCpuPkg BaseUefiCpuLib: Convert Ia32/InitializeFpu.asm to NASM

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / SmmProfile.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index 71fff0e5b0b628df2b6d26e8436d2e48840e80a7..f9cea55d9dcf6a781880fdbc45444992174b8399 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -934,8 +934,9 @@ CheckFeatureSupported (
   IN OUT VOID   *Buffer\r
   )\r
 {\r
-  UINT32                 RegEax;\r
-  UINT32                 RegEdx;\r
+  UINT32                         RegEax;\r
+  UINT32                         RegEdx;\r
+  MSR_IA32_MISC_ENABLE_REGISTER  MiscEnableMsr;\r
 \r
   if (mXdSupported) {\r
     AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r
@@ -966,10 +967,10 @@ CheckFeatureSupported (
       //    BTINT bits in the MSR_DEBUGCTLA MSR.\r
       // 2. The IA32_DS_AREA MSR can be programmed to point to the DS save area.\r
       //\r
-      if ((AsmMsrBitFieldRead64 (MSR_IA32_MISC_ENABLE, 11, 11) == 0) &&\r
-          (AsmMsrBitFieldRead64 (MSR_IA32_MISC_ENABLE, 12, 12) == 0)) {\r
+      MiscEnableMsr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);\r
+      if (MiscEnableMsr.Bits.BTS == 1) {\r
         //\r
-        // BTS facilities is supported.\r
+        // BTS facilities is not supported if MSR_IA32_MISC_ENABLE.BTS bit is set.\r
         //\r
         mBtsSupported = FALSE;\r
       }\r
@@ -1072,8 +1073,6 @@ ActivateLBR (
   if ((DebugCtl & MSR_DEBUG_CTL_LBR) != 0) {\r
     return ;\r
   }\r
-  AsmWriteMsr64 (MSR_LER_FROM_LIP, 0);\r
-  AsmWriteMsr64 (MSR_LER_TO_LIP, 0);\r
   DebugCtl |= MSR_DEBUG_CTL_LBR;\r
   AsmWriteMsr64 (MSR_DEBUG_CTL, DebugCtl);\r
 }\r