;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; Variables referenced by C code\r
;\r
EXTERNDEF SmiRendezvous:PROC\r
+EXTERNDEF CpuSmmDebugEntry:PROC\r
+EXTERNDEF CpuSmmDebugExit:PROC\r
EXTERNDEF gcSmiHandlerTemplate:BYTE\r
EXTERNDEF gcSmiHandlerSize:WORD\r
EXTERNDEF gSmiCr3:DWORD\r
EXTERNDEF gSmiStack:DWORD\r
EXTERNDEF gSmbase:DWORD\r
-EXTERNDEF FeaturePcdGet (PcdCpuSmmDebug):BYTE\r
+EXTERNDEF mXdSupported:BYTE\r
EXTERNDEF gSmiHandlerIdtr:FWORD\r
\r
+MSR_IA32_MISC_ENABLE EQU 1A0h\r
+MSR_EFER EQU 0c0000080h\r
+MSR_EFER_XD EQU 0800h\r
\r
;\r
; Constants relating to PROCESSOR_SMM_DESCRIPTOR\r
mov eax, TSS_SEGMENT\r
ltr ax\r
\r
+; enable NXE if supported\r
+ DB 0b0h ; mov al, imm8\r
+mXdSupported DB 1\r
+ cmp al, 0\r
+ jz @SkipXd\r
+;\r
+; Check XD disable bit\r
+;\r
+ mov ecx, MSR_IA32_MISC_ENABLE\r
+ rdmsr\r
+ sub esp, 4\r
+ push rdx ; save MSR_IA32_MISC_ENABLE[63-32]\r
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
+ jz @f\r
+ and dx, 0FFFBh ; clear XD Disable bit if it is set\r
+ wrmsr\r
+@@:\r
+ mov ecx, MSR_EFER\r
+ rdmsr\r
+ or ax, MSR_EFER_XD ; enable NXE\r
+ wrmsr\r
+ jmp @XdDone\r
+@SkipXd:\r
+ sub esp, 8\r
+@XdDone:\r
+\r
; Switch into @LongMode\r
push LONG_MODE_CS ; push cs hardcore here\r
call Base ; push return address for retf later\r
Base:\r
add dword ptr [rsp], @LongMode - Base; offset for far retf, seg is the 1st arg\r
- mov ecx, 0c0000080h\r
+\r
+ mov ecx, MSR_EFER\r
rdmsr\r
- or ah, 1\r
+ or ah, 1 ; enable LME\r
wrmsr\r
mov rbx, cr0\r
- bts ebx, 31\r
+ or ebx, 080010023h ; enable paging + WP + NE + MP + PE\r
mov cr0, rbx\r
retf\r
@LongMode: ; long mode (64-bit code) starts here\r
; jmp _SmiHandler ; instruction is not needed\r
\r
_SmiHandler:\r
-;\r
-; The following lines restore DR6 & DR7 before running C code. They are useful\r
-; when you want to enable hardware breakpoints in SMM.\r
-;\r
-; NOTE: These lines might not be appreciated in runtime since they might\r
-; conflict with OS debugging facilities. Turn them off in RELEASE.\r
-;\r
- mov rax, offset FeaturePcdGet (PcdCpuSmmDebug) ;Get absolute address. Avoid RIP relative addressing\r
- cmp byte ptr [rax], 0\r
- jz @1\r
-\r
- DB 48h, 8bh, 0dh ; mov rcx, [rip + disp32]\r
- DD SSM_DR6 - ($ + 4 - _SmiEntryPoint + 8000h)\r
- DB 48h, 8bh, 15h ; mov rdx, [rip + disp32]\r
- DD SSM_DR7 - ($ + 4 - _SmiEntryPoint + 8000h)\r
- mov dr6, rcx\r
- mov dr7, rdx\r
-@1:\r
- mov rcx, [rsp] ; rcx <- CpuIndex\r
- mov rax, SmiRendezvous ; rax <- absolute addr of SmiRedezvous\r
+ mov rbx, [rsp] ; rbx <- CpuIndex\r
\r
;\r
; Save FP registers\r
;\r
- sub rsp, 208h\r
+ sub rsp, 200h\r
DB 48h ; FXSAVE64\r
fxsave [rsp]\r
\r
add rsp, -20h\r
+\r
+ mov rcx, rbx\r
+ mov rax, CpuSmmDebugEntry\r
+ call rax\r
+\r
+ mov rcx, rbx\r
+ mov rax, SmiRendezvous ; rax <- absolute addr of SmiRedezvous\r
+ call rax\r
+\r
+ mov rcx, rbx\r
+ mov rax, CpuSmmDebugExit\r
call rax\r
+\r
add rsp, 20h\r
\r
;\r
DB 48h ; FXRSTOR64\r
fxrstor [rsp]\r
\r
- mov rax, offset FeaturePcdGet (PcdCpuSmmDebug) ;Get absolute address. Avoid RIP relative addressing\r
- cmp byte ptr [rax], 0\r
- jz @2\r
-\r
- mov rdx, dr7\r
- mov rcx, dr6\r
- DB 48h, 89h, 15h ; mov [rip + disp32], rdx\r
- DD SSM_DR7 - ($ + 4 - _SmiEntryPoint + 8000h)\r
- DB 48h, 89h, 0dh ; mov [rip + disp32], rcx\r
- DD SSM_DR6 - ($ + 4 - _SmiEntryPoint + 8000h)\r
-@2:\r
+ add rsp, 200h\r
+\r
+ mov rax, offset ASM_PFX(mXdSupported)\r
+ mov al, [rax]\r
+ cmp al, 0\r
+ jz @f\r
+ pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r
+ test edx, BIT2\r
+ jz @f\r
+ mov ecx, MSR_IA32_MISC_ENABLE\r
+ rdmsr\r
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r
+ wrmsr\r
+\r
+@@:\r
rsm\r
\r
gcSmiHandlerSize DW $ - _SmiEntryPoint\r