UefiCpuPkg/PiSmmCpuDxeSmm: TransferApToSafeState() use UINTN params

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmmProfileArch.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
index c4ec12debb1c444555564dde20b63ab077afa54b..cc393dcd894e126b3666f56058487c45415b17ec 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
@@ -1,7 +1,7 @@
 /** @file\r
 X64 processor specific functions to enable SMM profile.\r
 \r
-Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -45,13 +45,14 @@ InitSmmS3Cr3 (
   //\r
   // Generate PAE page table for the first 4GB memory space\r
   //\r
-  Pages = Gen4GPageTable (1);\r
+  Pages = Gen4GPageTable (FALSE);\r
 \r
   //\r
   // Fill Page-Table-Level4 (PML4) entry\r
   //\r
-  PTEntry = (UINT64*)(UINTN)(Pages - EFI_PAGES_TO_SIZE (1));\r
-  *PTEntry = Pages + IA32_PG_P;\r
+  PTEntry = (UINT64*)AllocatePageTableMemory (1);\r
+  ASSERT (PTEntry != NULL);\r
+  *PTEntry = Pages | PAGE_ATTRIBUTE_BITS;\r
   ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));\r
 \r
   //\r
@@ -78,7 +79,7 @@ InitPagesForPFHandler (
   //\r
   Address = NULL;\r
   Address = AllocatePages (MAX_PF_PAGE_COUNT);\r
-  ASSERT_EFI_ERROR (Address != NULL);\r
+  ASSERT (Address != NULL);\r
 \r
   mPFPageBuffer =  (UINT64)(UINTN) Address;\r
   mPFPageIndex = 0;\r
@@ -117,7 +118,7 @@ AcquirePage (
   //\r
   // Link & Record the current uplink\r
   //\r
-  *Uplink = Address | IA32_PG_P | IA32_PG_RW;\r
+  *Uplink = Address | PAGE_ATTRIBUTE_BITS;\r
   mPFPageUplink[mPFPageIndex] = Uplink;\r
 \r
   mPFPageIndex = (mPFPageIndex + 1) % MAX_PF_PAGE_COUNT;\r
@@ -242,9 +243,9 @@ RestorePageTableAbove4G (
       // PTE\r
       PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
       for (Index = 0; Index < 512; Index++) {\r
-        PageTable[Index] = Address | IA32_PG_RW | IA32_PG_P;\r
+        PageTable[Index] = Address | PAGE_ATTRIBUTE_BITS;\r
         if (!IsAddressValid (Address, &Nx)) {\r
-          PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));\r
+          PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
         }\r
         if (Nx && mXdSupported) {\r
           PageTable[Index] = PageTable[Index] | IA32_PG_NX;\r
@@ -262,7 +263,7 @@ RestorePageTableAbove4G (
         //\r
         // Patch to remove present flag and rw flag.\r
         //\r
-        PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));\r
+        PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
       }\r
       //\r
       // Set XD bit to 1\r
@@ -289,7 +290,7 @@ RestorePageTableAbove4G (
   //\r
   // Add present flag or clear XD flag to make page fault handler succeed.\r
   //\r
-  PageTable[PTIndex] |= (UINT64)(IA32_PG_RW | IA32_PG_P);\r
+  PageTable[PTIndex] |= (UINT64)(PAGE_ATTRIBUTE_BITS);\r
   if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r
     //\r
     // If page fault is caused by instruction fetch, clear XD bit in the entry.\r