UefiCpuPkg/PiSmmCpuDxeSmm: Add paging protection.

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmmProfileArch.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
index b3cd629f5576e3633f7b80d56fbbb649d843773c..cc393dcd894e126b3666f56058487c45415b17ec 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
@@ -1,7 +1,7 @@
 /** @file\r
 X64 processor specific functions to enable SMM profile.\r
 \r
-Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -45,12 +45,13 @@ InitSmmS3Cr3 (
   //\r
   // Generate PAE page table for the first 4GB memory space\r
   //\r
-  Pages = Gen4GPageTable (1);\r
+  Pages = Gen4GPageTable (FALSE);\r
 \r
   //\r
   // Fill Page-Table-Level4 (PML4) entry\r
   //\r
-  PTEntry = (UINT64*)(UINTN)(Pages - EFI_PAGES_TO_SIZE (1));\r
+  PTEntry = (UINT64*)AllocatePageTableMemory (1);\r
+  ASSERT (PTEntry != NULL);\r
   *PTEntry = Pages | PAGE_ATTRIBUTE_BITS;\r
   ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));\r
 \r
@@ -78,7 +79,7 @@ InitPagesForPFHandler (
   //\r
   Address = NULL;\r
   Address = AllocatePages (MAX_PF_PAGE_COUNT);\r
-  ASSERT_EFI_ERROR (Address != NULL);\r
+  ASSERT (Address != NULL);\r
 \r
   mPFPageBuffer =  (UINT64)(UINTN) Address;\r
   mPFPageIndex = 0;\r