// will be built based on them in PEI phase.\r
//\r
SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);\r
- SecCoreData->PeiTemporaryRamSize &= ~0x07;\r
+ SecCoreData->PeiTemporaryRamSize &= ~(UINTN)0x07;\r
} else {\r
//\r
// No addition PPI, PpiList directly point to the common PPI list.\r