UefiCpuPkg SecCore: Adjust PeiTemporaryRamBase&Size to be 8byte aligned

[mirror_edk2.git] / UefiCpuPkg / SecCore / SecMain.c

diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c
index af1e661a307a9e871bdb6f56116ee6feeb11dbbc..18b7782bb87d905ff8fb98943e9c90d2e4973aed 100644 (file)
--- a/UefiCpuPkg/SecCore/SecMain.c
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -1,7 +1,7 @@
 /** @file\r
   C functions in SEC\r
 \r
-  Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -230,6 +230,12 @@ SecStartupPhase2(
     ASSERT (SecCoreData->PeiTemporaryRamSize > Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
     SecCoreData->PeiTemporaryRamBase = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
     SecCoreData->PeiTemporaryRamSize = SecCoreData->PeiTemporaryRamSize - Index * sizeof (EFI_PEI_PPI_DESCRIPTOR);\r
+    //\r
+    // Adjust the Base and Size to be 8-byte aligned as HOB which has 8byte aligned requirement\r
+    // will be built based on them in PEI phase.\r
+    //\r
+    SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);\r
+    SecCoreData->PeiTemporaryRamSize &= ~0x07;\r
   } else {\r
     //\r
     // No addition PPI, PpiList directly point to the common PPI list.\r
@@ -237,6 +243,14 @@ SecStartupPhase2(
     PpiList = &mPeiSecPlatformInformationPpi[0];\r
   }\r
 \r
+  DEBUG ((\r
+    DEBUG_INFO,\r
+    "%a() Stack Base: 0x%p, Stack Size: 0x%x\n",\r
+    __FUNCTION__,\r
+    SecCoreData->StackBase,\r
+    (UINT32) SecCoreData->StackSize\r
+    ));\r
+\r
   //\r
   // Report Status Code to indicate transferring to PEI core\r
   //\r