## @file UefiCpuPkg.dec\r
# This Package provides UEFI compatible CPU modules and libraries.\r
#\r
-# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>\r
#\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
##\r
MpInitLib|Include/Library/MpInitLib.h\r
\r
+ ## @libraryclass Provides function to support VMGEXIT processing.\r
+ VmgExitLib|Include/Library/VmgExitLib.h\r
+\r
+ ## @libraryclass Provides function to get CPU cache information.\r
+ CpuCacheInfoLib|Include/Library/CpuCacheInfoLib.h\r
+\r
+ ## @libraryclass Provides function for loading microcode.\r
+ MicrocodeLib|Include/Library/MicrocodeLib.h\r
+\r
[Guids]\r
gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}\r
gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}\r
## Include/Guid/CpuFeaturesInitDone.h\r
gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}\r
\r
+ ## Include/Guid/MicrocodePatchHob.h\r
+ gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}\r
+\r
[Protocols]\r
## Include/Protocol/SmmCpuService.h\r
gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}\r
[Ppis]\r
gEdkiiPeiMpServices2PpiGuid = { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}\r
\r
+ ## Include/Ppi/ShadowMicrocode.h\r
+ gEdkiiPeiShadowMicrocodePpiGuid = { 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 }}\r
+\r
+ ## Include/Ppi/RepublishSecPpi.h\r
+ gRepublishSecPpiPpiGuid = { 0x27a71b1e, 0x73ee, 0x43d6, { 0xac, 0xe3, 0x52, 0x1a, 0x2d, 0xc5, 0xd0, 0x92 }}\r
+\r
[PcdsFeatureFlag]\r
## Indicates if SMM Profile will be enabled.\r
# If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\r
- # It could not be enabled at the same time with SMM static page table feature (PcdCpuSmmStaticPageTable).\r
+ # In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.\r
+ # In IA32 build, the page table memory is not marked as read-only when it is enabled.\r
# This PCD is only for validation purpose. It should be set to false in production.<BR><BR>\r
# TRUE - SMM Profile will be enabled.<BR>\r
# FALSE - SMM Profile will be disabled.<BR>\r
# @Prompt Specify size of good stack of exception which need switching stack.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001\r
\r
+ ## Count of pre allocated SMM MP tokens per chunk.\r
+ # @Prompt Specify the count of pre allocated SMM MP tokens per chunk.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x30002002\r
+\r
+ ## Area of memory where the SEV-ES work area block lives.\r
+ # @Prompt Configure the SEV-ES work area base\r
+ gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase|0x0|UINT32|0x30002005\r
+\r
+ ## Size of teh area of memory where the SEV-ES work area block lives.\r
+ # @Prompt Configure the SEV-ES work area base\r
+ gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize|0x0|UINT32|0x30002006\r
+\r
[PcdsFixedAtBuild, PcdsPatchableInModule]\r
## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.\r
# @Prompt Configure base address of CPU Local APIC\r
# @Prompt If CPU features will be initialized during S3 resume.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D\r
\r
+ ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.\r
+ # TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.\r
+ # Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)\r
+ # 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)\r
+ # Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)\r
+ # @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113\r
+\r
+ ## Specifies the periodic interval value in microseconds for the status check\r
+ # of APs for StartupAllAPs() and StartupThisAP() executed in non-blocking\r
+ # mode in DXE phase.\r
+ # @Prompt Periodic interval value in microseconds for AP status check in DXE.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds|100000|UINT32|0x0000001E\r
+\r
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
## Specifies max supported number of Logical Processors.\r
# @Prompt Configure max supported number of Logical Processors\r
## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.\r
# @Prompt Timeout for the BSP to detect all APs for the first time.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004\r
+ ## Specifies the number of Logical Processors that are available in the\r
+ # preboot environment after platform reset, including BSP and APs. Possible\r
+ # values:<BR><BR>\r
+ # zero (default) - PcdCpuBootLogicalProcessorNumber is ignored, and\r
+ # PcdCpuApInitTimeOutInMicroSeconds limits the initial AP\r
+ # detection by the BSP.<BR>\r
+ # nonzero - PcdCpuApInitTimeOutInMicroSeconds is ignored. The initial\r
+ # AP detection finishes only when the detected CPU count\r
+ # (BSP plus APs) reaches the value of\r
+ # PcdCpuBootLogicalProcessorNumber, regardless of how long\r
+ # that takes.<BR>\r
+ # @Prompt Number of Logical Processors available after platform reset.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber|0|UINT32|0x00000008\r
## Specifies the base address of the first microcode Patch in the microcode Region.\r
# @Prompt Microcode Region base address.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005\r
# @Prompt The specified AP target C-state for Mwait.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007\r
\r
- ## Indicates if SMM uses static page table.\r
- # If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.\r
- # This flag only impacts X64 build, because SMM always builds static page table for IA32.\r
- # It could not be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\r
- # It could not be enabled also at the same time with heap guard feature for SMM\r
- # (PcdHeapGuardPropertyMask in MdeModulePkg).<BR><BR>\r
- # TRUE - SMM uses static page table for all memory.<BR>\r
- # FALSE - SMM uses static page table for below 4G memory and use on-demand paging for above 4G memory.<BR>\r
- # @Prompt Use static page table for all memory in SMM.\r
- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable|TRUE|BOOLEAN|0x3213210D\r
-\r
## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.\r
# @Prompt AP synchronization timeout value in SMM.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104\r
# @Prompt Current boot is a power-on reset.\r
gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B\r
\r
+[PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]\r
+ ## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r
+ # MMIO access is always allowed regardless of the value of this PCD.\r
+ # Loose of such restriction is only required by RAS components in X64 platforms.\r
+ # The PCD value is considered as constantly TRUE in IA32 platforms.\r
+ # When the PCD value is TRUE, page table is initialized to cover all memory spaces\r
+ # and the memory occupied by page table is protected by page table itself as read-only.\r
+ # In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\r
+ # In X64 build, it could not be enabled also at the same time with heap guard feature for SMM\r
+ # (PcdHeapGuardPropertyMask in MdeModulePkg).\r
+ # In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)\r
+ # or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.\r
+ # TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>\r
+ # FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>\r
+ # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F\r
+\r
[PcdsDynamic, PcdsDynamicEx]\r
## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.\r
# @Prompt The pointer to a CPU S3 data buffer.\r
# @ValidRange 0x80000001 | 0 - 1\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015\r
\r
+ ## This dynamic PCD indicates whether SEV-ES is enabled\r
+ # TRUE - SEV-ES is enabled\r
+ # FALSE - SEV-ES is not enabled\r
+ # @Prompt SEV-ES Status\r
+ gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|FALSE|BOOLEAN|0x60000016\r
+\r
[UserExtensions.TianoCore."ExtraFiles"]\r
UefiCpuPkgExtra.uni\r