## @file UefiCpuPkg.dec\r
# This Package provides UEFI compatible CPU modules and libraries.\r
#\r
-# Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>\r
#\r
-# This program and the accompanying materials are licensed and made available under\r
-# the terms and conditions of the BSD License which accompanies this distribution.\r
-# The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
##\r
\r
PACKAGE_NAME = UefiCpuPkg\r
PACKAGE_UNI_FILE = UefiCpuPkg.uni\r
PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23\r
- PACKAGE_VERSION = 0.80\r
+ PACKAGE_VERSION = 0.90\r
\r
[Includes]\r
Include\r
##\r
MpInitLib|Include/Library/MpInitLib.h\r
\r
- ## @libraryclass Provides services to access Microcode region on flash device.\r
- #\r
- MicrocodeFlashAccessLib|Include/Library/MicrocodeFlashAccessLib.h\r
-\r
[Guids]\r
gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}\r
gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}\r
\r
- ## Include/Guid/MicrocodeFmp.h\r
- gMicrocodeFmpImageTypeIdGuid = { 0x96d4fdcd, 0x1502, 0x424d, { 0x9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } }\r
-\r
## Include/Guid/CpuFeaturesSetDone.h\r
gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}\r
\r
## Include/Guid/CpuFeaturesInitDone.h\r
gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}\r
\r
+ ## Include/Guid/MicrocodePatchHob.h\r
+ gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}\r
+\r
[Protocols]\r
## Include/Protocol/SmmCpuService.h\r
gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}\r
# 0x80000001 | Invalid value provided.\r
#\r
\r
+[Ppis]\r
+ gEdkiiPeiMpServices2PpiGuid = { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}\r
+\r
[PcdsFeatureFlag]\r
## Indicates if SMM Profile will be enabled.\r
# If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\r
+ # In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.\r
+ # In IA32 build, the page table memory is not marked as read-only when it is enabled.\r
# This PCD is only for validation purpose. It should be set to false in production.<BR><BR>\r
# TRUE - SMM Profile will be enabled.<BR>\r
# FALSE - SMM Profile will be disabled.<BR>\r
# @Prompt Lock SMM Feature Control MSR.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B\r
\r
+ ## Indicates if FIT based microcode shadowing will be enabled.<BR><BR>\r
+ # TRUE - FIT base microcode shadowing will be enabled.<BR>\r
+ # FALSE - FIT base microcode shadowing will be disabled.<BR>\r
+ # @Prompt FIT based microcode shadowing.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuShadowMicrocodeByFit|FALSE|BOOLEAN|0x3213210D\r
+\r
+[PcdsFixedAtBuild]\r
+ ## List of exception vectors which need switching stack.\r
+ # This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
+ # By default exception #DD(8), #PF(14) are supported.\r
+ # @Prompt Specify exception vectors which need switching stack.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000\r
+\r
+ ## Size of good stack for an exception.\r
+ # This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
+ # @Prompt Specify size of good stack of exception which need switching stack.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001\r
+\r
+ ## Count of pre allocated SMM MP tokens per chunk.\r
+ # @Prompt Specify the count of pre allocated SMM MP tokens per chunk.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x30002002\r
+\r
[PcdsFixedAtBuild, PcdsPatchableInModule]\r
## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.\r
# @Prompt Configure base address of CPU Local APIC\r
# @Prompt Processor stack size in SMM.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105\r
\r
+ ## Specifies shadow stack size in bytes for each processor in SMM.\r
+ # @Prompt Processor shadow stack size in SMM.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x2000|UINT32|0x3213210E\r
+\r
## Indicates if SMM Code Access Check is enabled.\r
# If enabled, the SMM handler cannot execute the code outside SMM regions.\r
# This PCD is suggested to TRUE in production image.<BR><BR>\r
# @Prompt If CPU features will be initialized during S3 resume.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D\r
\r
+ ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.\r
+ # TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.\r
+ # Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)\r
+ # 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)\r
+ # Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)\r
+ # @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113\r
+\r
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
## Specifies max supported number of Logical Processors.\r
# @Prompt Configure max supported number of Logical Processors\r
## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.\r
# @Prompt Timeout for the BSP to detect all APs for the first time.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004\r
+ ## Specifies the number of Logical Processors that are available in the\r
+ # preboot environment after platform reset, including BSP and APs. Possible\r
+ # values:<BR><BR>\r
+ # zero (default) - PcdCpuBootLogicalProcessorNumber is ignored, and\r
+ # PcdCpuApInitTimeOutInMicroSeconds limits the initial AP\r
+ # detection by the BSP.<BR>\r
+ # nonzero - PcdCpuApInitTimeOutInMicroSeconds is ignored. The initial\r
+ # AP detection finishes only when the detected CPU count\r
+ # (BSP plus APs) reaches the value of\r
+ # PcdCpuBootLogicalProcessorNumber, regardless of how long\r
+ # that takes.<BR>\r
+ # @Prompt Number of Logical Processors available after platform reset.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber|0|UINT32|0x00000008\r
## Specifies the base address of the first microcode Patch in the microcode Region.\r
# @Prompt Microcode Region base address.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005\r
# @Prompt The specified AP target C-state for Mwait.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007\r
\r
- ## Indicates if SMM uses static page table.\r
- # If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.<BR><BR>\r
- # This flag only impacts X64 build, because SMM alway builds static page table for IA32.\r
- # TRUE - SMM uses static page table for all memory.<BR>\r
- # FALSE - SMM uses static page table for below 4G memory and use on-demand paging for above 4G memory.<BR>\r
- # @Prompt Use static page table for all memory in SMM.\r
- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable|TRUE|BOOLEAN|0x3213210D\r
-\r
## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.\r
# @Prompt AP synchronization timeout value in SMM.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104\r
# @Prompt SMM CPU Synchronization Method.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014\r
\r
- ## Specifies user's desired settings for enabling/disabling processor features.\r
- # @Prompt User settings for enabling/disabling processor features.\r
- gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesUserConfiguration|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000017\r
-\r
## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.\r
# @Prompt The encoded values for target duty cycle modulation.\r
# @ValidRange 0x80000001 | 0 - 15\r
# @Prompt Current boot is a power-on reset.\r
gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B\r
\r
+[PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]\r
+ ## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r
+ # MMIO access is always allowed regardless of the value of this PCD.\r
+ # Loose of such restriction is only required by RAS components in X64 platforms.\r
+ # The PCD value is considered as constantly TRUE in IA32 platforms.\r
+ # When the PCD value is TRUE, page table is initialized to cover all memory spaces\r
+ # and the memory occupied by page table is protected by page table itself as read-only.\r
+ # In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\r
+ # In X64 build, it could not be enabled also at the same time with heap guard feature for SMM\r
+ # (PcdHeapGuardPropertyMask in MdeModulePkg).\r
+ # In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)\r
+ # or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.\r
+ # TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>\r
+ # FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>\r
+ # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F\r
+\r
[PcdsDynamic, PcdsDynamicEx]\r
## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.\r
# @Prompt The pointer to a CPU S3 data buffer.\r
# @ValidList 0x80000001 | 0\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018\r
\r
- ## Specifies actual settings for processor features, each bit corresponding to a specific feature.\r
- # @Prompt Actual processor feature settings.\r
+ ## As input, specifies user's desired settings for enabling/disabling processor features.\r
+ ## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.\r
+ # @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.\r
# @ValidList 0x80000001 | 0\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019\r
\r
+ ## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>\r
+ # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
+ # This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
+ # Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>\r
+ # 0x0 - 4K.<BR>\r
+ # 0x1 - 8K.<BR>\r
+ # 0x2 - 16K.<BR>\r
+ # 0x3 - 32K.<BR>\r
+ # 0x4 - 64K.<BR>\r
+ # 0x5 - 128K.<BR>\r
+ # 0x6 - 256K.<BR>\r
+ # 0x7 - 512K.<BR>\r
+ # 0x8 - 1M.<BR>\r
+ # 0x9 - 2M.<BR>\r
+ # 0xA - 4M.<BR>\r
+ # 0xB - 8M.<BR>\r
+ # 0xC - 16M.<BR>\r
+ # 0xD - 32M.<BR>\r
+ # 0xE - 64M.<BR>\r
+ # 0xF - 128M.<BR>\r
+ # @Prompt The memory size used for processor trace if processor trace is enabled.\r
+ # @ValidRange 0x80000001 | 0 - 0xF\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012\r
+\r
+ ## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>\r
+ # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
+ # This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
+ # Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>\r
+ # 0 - Single Range output scheme.<BR>\r
+ # 1 - ToPA(Table of physical address) scheme.<BR>\r
+ # @Prompt The processor trace output scheme used when processor trace is enabled.\r
+ # @ValidRange 0x80000001 | 0 - 1\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015\r
+\r
[UserExtensions.TianoCore."ExtraFiles"]\r
UefiCpuPkgExtra.uni\r