arm64: Add workaround for Cavium Thunder erratum 30115

[mirror_ubuntu-zesty-kernel.git] / arch / arm64 / kernel / cpu_errata.c

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 2ed2a7657711c54df5e9f698868d936d309a8830..0e27f86ee70976b82cce63ce0b475eb94c2c606b 100644 (file)
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -132,6 +132,27 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
                .capability = ARM64_WORKAROUND_CAVIUM_27456,
                MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
        },
+#endif
+#ifdef CONFIG_CAVIUM_ERRATUM_30115
+       {
+       /* Cavium ThunderX, T88 pass 1.x - 2.2 */
+               .desc = "Cavium erratum 30115",
+               .capability = ARM64_WORKAROUND_CAVIUM_30115,
+               MIDR_RANGE(MIDR_THUNDERX, 0x00,
+                          (1 << MIDR_VARIANT_SHIFT) | 2),
+       },
+       {
+       /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
+               .desc = "Cavium erratum 30115",
+               .capability = ARM64_WORKAROUND_CAVIUM_30115,
+               MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x02),
+       },
+       {
+       /* Cavium ThunderX, T83 pass 1.0 */
+               .desc = "Cavium erratum 30115",
+               .capability = ARM64_WORKAROUND_CAVIUM_30115,
+               MIDR_RANGE(MIDR_THUNDERX_83XX, 0x00, 0x00),
+       },
 #endif
        {
                .desc = "Mismatched cache line size",