import quincy beta 17.1.0

[ceph.git] / ceph / src / include / mempool.h

diff --git a/ceph/src/include/mempool.h b/ceph/src/include/mempool.h
index fe84f3b8f09704b7f8f3f0834251f436a5634786..08d8282fb2f0e53c8d5e033df71aecf6ae8a3ed1 100644 (file)
--- a/ceph/src/include/mempool.h
+++ b/ceph/src/include/mempool.h
@@ -201,7 +201,16 @@ enum {
   num_shards = 1 << num_shard_bits
 };
 
-// align shard to a cacheline
+//
+// Align shard to a cacheline.
+//
+// It would be possible to retrieve the value at runtime (for instance
+// with getconf LEVEL1_DCACHE_LINESIZE or grep -m1 cache_alignment
+// /proc/cpuinfo). It is easier to hard code the largest cache
+// linesize for all known processors (128 bytes). If the actual cache
+// linesize is smaller on a given processor, it will just waste a few
+// bytes.
+//
 struct shard_t {
   ceph::atomic<size_t> bytes = {0};
   ceph::atomic<size_t> items = {0};