update source to Ceph Pacific 16.2.2

[ceph.git] / ceph / src / spdk / dpdk / drivers / net / ice / base / ice_controlq.h

diff --git a/ceph/src/spdk/dpdk/drivers/net/ice/base/ice_controlq.h b/ceph/src/spdk/dpdk/drivers/net/ice/base/ice_controlq.h
index 182db6754039c1b71f9873c9897230775b1a1a8c..e5e0001788bc7dd6e9269e692cf5d8bcff6adc8c 100644 (file)
--- a/ceph/src/spdk/dpdk/drivers/net/ice/base/ice_controlq.h
+++ b/ceph/src/spdk/dpdk/drivers/net/ice/base/ice_controlq.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2019
+ * Copyright(c) 2001-2020 Intel Corporation
  */
 
 #ifndef _ICE_CONTROLQ_H_
@@ -7,7 +7,6 @@
 
 #include "ice_adminq_cmd.h"
 
-
 /* Maximum buffer lengths for all control queue types */
 #define ICE_AQ_MAX_BUF_LEN 4096
 #define ICE_MBXQ_MAX_BUF_LEN 4096
@@ -24,7 +23,7 @@
  */
 #define EXP_FW_API_VER_BRANCH          0x00
 #define EXP_FW_API_VER_MAJOR           0x01
-#define EXP_FW_API_VER_MINOR           0x03
+#define EXP_FW_API_VER_MINOR           0x05
 
 /* Different control queue types: These are mainly for SW consumption. */
 enum ice_ctl_q {
@@ -33,11 +32,14 @@ enum ice_ctl_q {
        ICE_CTL_Q_MAILBOX,
 };
 
-/* Control Queue default settings */
-#define ICE_CTL_Q_SQ_CMD_TIMEOUT       250  /* msecs */
+/* Control Queue timeout settings - max delay 250ms */
+#define ICE_CTL_Q_SQ_CMD_TIMEOUT       2500  /* Count 2500 times */
+#define ICE_CTL_Q_SQ_CMD_USEC          100   /* Check every 100usec */
+#define ICE_CTL_Q_ADMIN_INIT_TIMEOUT   10    /* Count 10 times */
+#define ICE_CTL_Q_ADMIN_INIT_MSEC      100   /* Check every 100msec */
 
 struct ice_ctl_q_ring {
-       void *dma_head;                 /* Virtual address to dma head */
+       void *dma_head;                 /* Virtual address to DMA head */
        struct ice_dma_mem desc_buf;    /* descriptor ring memory */
        void *cmd_buf;                  /* command buffer memory */
 
@@ -60,6 +62,7 @@ struct ice_ctl_q_ring {
        u32 bal;
        u32 len_mask;
        u32 len_ena_mask;
+       u32 len_crit_mask;
        u32 head_mask;
 };
 
@@ -81,6 +84,7 @@ struct ice_rq_event_info {
 /* Control Queue information */
 struct ice_ctl_q_info {
        enum ice_ctl_q qtype;
+       enum ice_aq_err rq_last_status; /* last status on receive queue */
        struct ice_ctl_q_ring rq;       /* receive queue */
        struct ice_ctl_q_ring sq;       /* send queue */
        u32 sq_cmd_timeout;             /* send queue cmd write back timeout */
@@ -88,10 +92,9 @@ struct ice_ctl_q_info {
        u16 num_sq_entries;             /* send queue depth */
        u16 rq_buf_size;                /* receive queue buffer size */
        u16 sq_buf_size;                /* send queue buffer size */
+       enum ice_aq_err sq_last_status; /* last status on send queue */
        struct ice_lock sq_lock;                /* Send queue lock */
        struct ice_lock rq_lock;                /* Receive queue lock */
-       enum ice_aq_err sq_last_status; /* last status on send queue */
-       enum ice_aq_err rq_last_status; /* last status on receive queue */
 };
 
 #endif /* _ICE_CONTROLQ_H_ */