update source to Ceph Pacific 16.2.2

[ceph.git] / ceph / src / spdk / dpdk / drivers / net / sfc / base / hunt_nic.c

diff --git a/ceph/src/spdk/dpdk/drivers/net/sfc/base/hunt_nic.c b/ceph/src/spdk/dpdk/drivers/net/sfc/base/hunt_nic.c
index 054d4f432f6143f4e397f622094d2be741ca4f11..75c90500701052ce3f807ab661b5fbd6c8deef56 100644 (file)
--- a/ceph/src/spdk/dpdk/drivers/net/sfc/base/hunt_nic.c
+++ b/ceph/src/spdk/dpdk/drivers/net/sfc/base/hunt_nic.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
- * Copyright (c) 2012-2018 Solarflare Communications Inc.
- * All rights reserved.
+ * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2012-2019 Solarflare Communications Inc.
  */
 
 #include "efx.h"
@@ -72,7 +72,6 @@ hunt_board_cfg(
 {
        efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
        efx_port_t *epp = &(enp->en_port);
-       uint32_t flags;
        uint32_t sysclk, dpcpu_clk;
        uint32_t bandwidth;
        efx_rc_t rc;
@@ -130,43 +129,9 @@ hunt_board_cfg(
                encp->enc_bug41750_workaround = B_TRUE;
        }
 
-       /*
-        * If the bug26807 workaround is enabled, then firmware has enabled
-        * support for chained multicast filters. Firmware will reset (FLR)
-        * functions which have filters in the hardware filter table when the
-        * workaround is enabled/disabled.
-        *
-        * We must recheck if the workaround is enabled after inserting the
-        * first hardware filter, in case it has been changed since this check.
-        */
-       rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
-           B_TRUE, &flags);
-       if (rc == 0) {
-               encp->enc_bug26807_workaround = B_TRUE;
-               if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
-                       /*
-                        * Other functions had installed filters before the
-                        * workaround was enabled, and they have been reset
-                        * by firmware.
-                        */
-                       EFSYS_PROBE(bug26807_workaround_flr_done);
-                       /* FIXME: bump MC warm boot count ? */
-               }
-       } else if (rc == EACCES) {
-               /*
-                * Unprivileged functions cannot enable the workaround in older
-                * firmware.
-                */
-               encp->enc_bug26807_workaround = B_FALSE;
-       } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
-               encp->enc_bug26807_workaround = B_FALSE;
-       } else {
-               goto fail3;
-       }
-
        /* Get clock frequencies (in MHz). */
        if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
-               goto fail4;
+               goto fail3;
 
        /*
         * The Huntington timer quantum is 1536 sysclk cycles, documented for
@@ -215,7 +180,7 @@ hunt_board_cfg(
        encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
 
        if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
-               goto fail5;
+               goto fail4;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
 
        /* All Huntington devices have a PCIe Gen3, 8 lane connector */
@@ -223,8 +188,6 @@ hunt_board_cfg(
 
        return (0);
 
-fail5:
-       EFSYS_PROBE(fail5);
 fail4:
        EFSYS_PROBE(fail4);
 fail3: