import 15.2.0 Octopus source

[ceph.git] / ceph / src / spdk / intel-ipsec-mb / aes_cmac_subkey_gen.asm

diff --git a/ceph/src/spdk/intel-ipsec-mb/aes_cmac_subkey_gen.asm b/ceph/src/spdk/intel-ipsec-mb/aes_cmac_subkey_gen.asm
index 0ccdeaea4258127b8b17926d43b8ba2fdf78f3e6..7577c191293d04e6227d6b3e70feb836434c7a38 100644 (file)
--- a/ceph/src/spdk/intel-ipsec-mb/aes_cmac_subkey_gen.asm
+++ b/ceph/src/spdk/intel-ipsec-mb/aes_cmac_subkey_gen.asm
@@ -26,6 +26,8 @@
 ;;
 
 %include "os.asm"
+%define NO_AESNI_RENAME
+%include "aesni_emu.inc"
 
 ;;; Routines to generate subkeys for AES-CMAC.
 ;;; See RFC 4493 for more details.
@@ -190,6 +192,62 @@ K2_msb_is_zero_sse:
         movdqu          [KEY2], XKEY2
        ret
 
+MKGLOBAL(aes_cmac_subkey_gen_sse_no_aesni,function,)
+align 32
+aes_cmac_subkey_gen_sse_no_aesni:
+        ;; Step 1.  L := AES-128(K, const_Zero) ;
+        movdqa          XL, [KEY_EXP + 16*0]    ; 0. ARK xor const_Zero
+       EMULATE_AESENC  XL, [KEY_EXP + 16*1]    ; 1. ENC
+       EMULATE_AESENC  XL, [KEY_EXP + 16*2]    ; 2. ENC
+       EMULATE_AESENC  XL, [KEY_EXP + 16*3]    ; 3. ENC
+       EMULATE_AESENC  XL, [KEY_EXP + 16*4]    ; 4. ENC
+       EMULATE_AESENC  XL, [KEY_EXP + 16*5]    ; 5. ENC
+       EMULATE_AESENC  XL, [KEY_EXP + 16*6]    ; 6. ENC
+       EMULATE_AESENC  XL, [KEY_EXP + 16*7]    ; 7. ENC
+       EMULATE_AESENC  XL, [KEY_EXP + 16*8]    ; 8. ENC
+       EMULATE_AESENC  XL, [KEY_EXP + 16*9]    ; 9. ENC
+       EMULATE_AESENCLAST XL, [KEY_EXP + 16*10]; 10. ENC
+
+        ;; Step 2.  if MSB(L) is equal to 0
+        ;;          then    K1 := L << 1 ;
+        ;;          else    K1 := (L << 1) XOR const_Rb ;
+        pshufb          XL, [rel byteswap_const]
+        movdqa          XKEY1, XL
+        psllq           XKEY1, 1
+        ptest           XL, [rel xmm_bit63]
+        jz              K1_no_carry_bit_sse2
+        ;; set carry bit
+        por             XKEY1, [rel xmm_bit64]
+K1_no_carry_bit_sse2:
+        ptest           XL, [rel xmm_bit127]
+        jz              K1_msb_is_zero_sse2
+        ;; XOR const_Rb
+        pxor            XKEY1, [rel const_Rb]
+K1_msb_is_zero_sse2:
+
+        ;; Step 3.  if MSB(K1) is equal to 0
+        ;;          then    K2 := K1 << 1 ;
+        ;;          else    K2 := (K1 << 1) XOR const_Rb ;
+        movdqa          XKEY2, XKEY1
+        psllq           XKEY2, 1
+        ptest           XKEY1, [rel xmm_bit63]
+        jz              K2_no_carry_bit_sse2
+        ;; set carry bit
+        por             XKEY2, [rel xmm_bit64]
+K2_no_carry_bit_sse2:
+        ptest           XKEY1, [rel xmm_bit127]
+        jz              K2_msb_is_zero_sse2
+        ;; XOR const_Rb
+        pxor            XKEY2, [rel const_Rb]
+K2_msb_is_zero_sse2:
+
+        ;; Step 4.  return K1, K2
+        pshufb          XKEY1, [rel byteswap_const]
+        pshufb          XKEY2, [rel byteswap_const]
+        movdqu          [KEY1], XKEY1
+        movdqu          [KEY2], XKEY2
+       ret
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;;
 ;;; void aes_cmac_subkey_gen_avx(const void *key_exp, void *key1, void *key2)
@@ -201,8 +259,12 @@ K2_msb_is_zero_sse:
 ;;; See aes_cmac_subkey_gen_sse() above for operation details
 
 MKGLOBAL(aes_cmac_subkey_gen_avx,function,)
+MKGLOBAL(aes_cmac_subkey_gen_avx2,function,)
+MKGLOBAL(aes_cmac_subkey_gen_avx512,function,)
 align 32
 aes_cmac_subkey_gen_avx:
+aes_cmac_subkey_gen_avx2:
+aes_cmac_subkey_gen_avx512:
         ;; Step 1.  L := AES-128(K, const_Zero) ;
         vmovdqa         XL, [KEY_EXP + 16*0]        ; 0. ARK xor const_Zero
         vaesenc         XL, [KEY_EXP + 16*1]        ; 1. ENC