#include "exec.h"
#include "disas.h"
+#if !defined(CONFIG_SOFTMMU)
+#undef EAX
+#undef ECX
+#undef EDX
+#undef EBX
+#undef ESP
+#undef EBP
+#undef ESI
+#undef EDI
+#undef EIP
+#include <signal.h>
+#include <sys/ucontext.h>
+#endif
+
int tb_invalidated_flag;
//#define DEBUG_EXEC
}
#endif
+/* exit the current TB from a signal handler. The host registers are
+ restored in a state compatible with the CPU emulator
+ */
+void cpu_resume_from_signal(CPUState *env1, void *puc)
+{
+#if !defined(CONFIG_SOFTMMU)
+ struct ucontext *uc = puc;
+#endif
+
+ env = env1;
+
+ /* XXX: restore cpu registers saved in host registers */
+
+#if !defined(CONFIG_SOFTMMU)
+ if (puc) {
+ /* XXX: use siglongjmp ? */
+ sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
+ }
+#endif
+ longjmp(env->jmp_env, 1);
+}
+
/* main execution loop */
int cpu_exec(CPUState *env1)
/* prepare setjmp context for exception handling */
for(;;) {
if (setjmp(env->jmp_env) == 0) {
+ env->current_tb = NULL;
/* if an exception is pending, we execute it here */
if (env->exception_index >= 0) {
if (env->exception_index >= EXCP_INTERRUPT) {
env->exception_is_int,
env->error_code,
env->exception_next_eip, 0);
+#elif defined(TARGET_PPC)
+ do_interrupt(env);
#endif
}
env->exception_index = -1;
(env->eflags & IF_MASK) &&
!(env->hflags & HF_INHIBIT_IRQ_MASK)) {
int intno;
- intno = cpu_x86_get_pic_interrupt(env);
- if (loglevel) {
+ env->interrupt_request &= ~CPU_INTERRUPT_HARD;
+ intno = cpu_get_pic_interrupt(env);
+ if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
}
do_interrupt(intno, 0, 0, 0, 1);
- env->interrupt_request &= ~CPU_INTERRUPT_HARD;
/* ensure that no TB jump will be modified as
the program flow was changed */
#ifdef __sparc__
T0 = 0;
#endif
}
+#elif defined(TARGET_PPC)
+#if 0
+ if ((interrupt_request & CPU_INTERRUPT_RESET)) {
+ cpu_ppc_reset(env);
+ }
+#endif
+ if (msr_ee != 0) {
+ if ((interrupt_request & CPU_INTERRUPT_HARD)) {
+ /* Raise it */
+ env->exception_index = EXCP_EXTERNAL;
+ env->error_code = 0;
+ do_interrupt(env);
+ env->interrupt_request &= ~CPU_INTERRUPT_HARD;
+ } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
+ /* Raise it */
+ env->exception_index = EXCP_DECR;
+ env->error_code = 0;
+ do_interrupt(env);
+ env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
+ }
+ }
#endif
+ if (interrupt_request & CPU_INTERRUPT_EXITTB) {
+ env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
+ /* ensure that no TB jump will be modified as
+ the program flow was changed */
+#ifdef __sparc__
+ tmp_T0 = 0;
+#else
+ T0 = 0;
+#endif
+ }
if (interrupt_request & CPU_INTERRUPT_EXIT) {
env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
env->exception_index = EXCP_INTERRUPT;
}
}
#ifdef DEBUG_EXEC
- if (loglevel) {
+ if (loglevel & CPU_LOG_EXEC) {
#if defined(TARGET_I386)
/* restore flags in standard format */
env->regs[R_EAX] = EAX;
pc = (uint8_t *)env->regs[15];
#elif defined(TARGET_SPARC)
flags = 0;
- cs_base = env->npc;
+ cs_base = (uint8_t *)env->npc;
pc = (uint8_t *) env->pc;
#elif defined(TARGET_PPC)
flags = 0;
tb->cs_base == (unsigned long)cs_base &&
tb->flags == flags) {
/* check next page if needed */
- virt_page2 = ((unsigned long)pc + tb->size - 1) & TARGET_PAGE_MASK;
- if (((unsigned long)pc & TARGET_PAGE_MASK) != virt_page2) {
+ if (tb->page_addr[1] != -1) {
+ virt_page2 = ((unsigned long)pc & TARGET_PAGE_MASK) +
+ TARGET_PAGE_SIZE;
phys_page2 = get_phys_addr_code(env, virt_page2);
if (tb->page_addr[1] == phys_page2)
goto found;
spin_unlock(&tb_lock);
}
#ifdef DEBUG_EXEC
- if (loglevel) {
+ if (loglevel & CPU_LOG_EXEC) {
fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
(long)tb->tc_ptr, (long)tb->pc,
lookup_symbol((void *)tb->pc));
T0 = tmp_T0;
#endif
/* see if we can patch the calling TB. */
- if (T0 != 0) {
+ if (T0 != 0
+#if defined(TARGET_I386) && defined(USE_CODE_COPY)
+ && (tb->cflags & CF_CODE_COPY) ==
+ (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
+#endif
+ ) {
spin_lock(&tb_lock);
tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
+#if defined(USE_CODE_COPY)
+ /* propagates the FP use info */
+ ((TranslationBlock *)(T0 & ~3))->cflags |=
+ (tb->cflags & CF_FP_USED);
+#endif
spin_unlock(&tb_lock);
}
tc_ptr = tb->tc_ptr;
: /* no outputs */
: "r" (gen_func)
: "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
+#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
+{
+ if (!(tb->cflags & CF_CODE_COPY)) {
+ if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
+ save_native_fp_state(env);
+ }
+ gen_func();
+ } else {
+ if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
+ restore_native_fp_state(env);
+ }
+ /* we work with native eflags */
+ CC_SRC = cc_table[CC_OP].compute_all();
+ CC_OP = CC_OP_EFLAGS;
+ asm(".globl exec_loop\n"
+ "\n"
+ "debug1:\n"
+ " pushl %%ebp\n"
+ " fs movl %10, %9\n"
+ " fs movl %11, %%eax\n"
+ " andl $0x400, %%eax\n"
+ " fs orl %8, %%eax\n"
+ " pushl %%eax\n"
+ " popf\n"
+ " fs movl %%esp, %12\n"
+ " fs movl %0, %%eax\n"
+ " fs movl %1, %%ecx\n"
+ " fs movl %2, %%edx\n"
+ " fs movl %3, %%ebx\n"
+ " fs movl %4, %%esp\n"
+ " fs movl %5, %%ebp\n"
+ " fs movl %6, %%esi\n"
+ " fs movl %7, %%edi\n"
+ " fs jmp *%9\n"
+ "exec_loop:\n"
+ " fs movl %%esp, %4\n"
+ " fs movl %12, %%esp\n"
+ " fs movl %%eax, %0\n"
+ " fs movl %%ecx, %1\n"
+ " fs movl %%edx, %2\n"
+ " fs movl %%ebx, %3\n"
+ " fs movl %%ebp, %5\n"
+ " fs movl %%esi, %6\n"
+ " fs movl %%edi, %7\n"
+ " pushf\n"
+ " popl %%eax\n"
+ " movl %%eax, %%ecx\n"
+ " andl $0x400, %%ecx\n"
+ " shrl $9, %%ecx\n"
+ " andl $0x8d5, %%eax\n"
+ " fs movl %%eax, %8\n"
+ " movl $1, %%eax\n"
+ " subl %%ecx, %%eax\n"
+ " fs movl %%eax, %11\n"
+ " fs movl %9, %%ebx\n" /* get T0 value */
+ " popl %%ebp\n"
+ :
+ : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
+ "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
+ "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
+ "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
+ "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
+ "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
+ "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
+ "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
+ "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
+ "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
+ "a" (gen_func),
+ "m" (*(uint8_t *)offsetof(CPUState, df)),
+ "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
+ : "%ecx", "%edx"
+ );
+ }
+}
#else
gen_func();
#endif
#if defined(TARGET_I386)
+#if defined(USE_CODE_COPY)
+ if (env->native_fp_regs) {
+ save_native_fp_state(env);
+ }
+#endif
/* restore flags in standard format */
env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
return ret;
}
+/* must only be called from the generated code as an exception can be
+ generated */
+void tb_invalidate_page_range(target_ulong start, target_ulong end)
+{
+ /* XXX: cannot enable it yet because it yields to MMU exception
+ where NIP != read address on PowerPC */
+#if 0
+ target_ulong phys_addr;
+ phys_addr = get_phys_addr_code(env, start);
+ tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
+#endif
+}
+
#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
#endif /* TARGET_I386 */
-#undef EAX
-#undef ECX
-#undef EDX
-#undef EBX
-#undef ESP
-#undef EBP
-#undef ESI
-#undef EDI
-#undef EIP
-#include <signal.h>
-#include <sys/ucontext.h>
+#if !defined(CONFIG_SOFTMMU)
#if defined(TARGET_I386)
write caused the exception and otherwise 0'. 'old_set' is the
signal set which should be restored */
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
- int is_write, sigset_t *old_set)
+ int is_write, sigset_t *old_set,
+ void *puc)
{
TranslationBlock *tb;
int ret;
if (cpu_single_env)
env = cpu_single_env; /* XXX: find a correct solution for multithread */
#if defined(DEBUG_SIGNAL)
- printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
- pc, address, is_write, *(unsigned long *)old_set);
+ qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
+ pc, address, is_write, *(unsigned long *)old_set);
#endif
/* XXX: locking issue */
- if (is_write && page_unprotect(address)) {
+ if (is_write && page_unprotect(address, pc, puc)) {
return 1;
}
+
/* see if it is an MMU fault */
ret = cpu_x86_handle_mmu_fault(env, address, is_write,
((env->hflags & HF_CPL_MASK) == 3), 0);
if (tb) {
/* the PC is inside the translated code. It means that we have
a virtual CPU fault */
- cpu_restore_state(tb, env, pc);
+ cpu_restore_state(tb, env, pc, puc);
}
if (ret == 1) {
#if 0
} else {
/* activate soft MMU for this block */
env->hflags |= HF_SOFTMMU_MASK;
- sigprocmask(SIG_SETMASK, old_set, NULL);
- cpu_loop_exit();
+ cpu_resume_from_signal(env, puc);
}
/* never comes here */
return 1;
#elif defined(TARGET_ARM)
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
- int is_write, sigset_t *old_set)
+ int is_write, sigset_t *old_set,
+ void *puc)
{
/* XXX: do more */
return 0;
}
#elif defined(TARGET_SPARC)
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
- int is_write, sigset_t *old_set)
+ int is_write, sigset_t *old_set,
+ void *puc)
{
/* XXX: locking issue */
- if (is_write && page_unprotect(address)) {
+ if (is_write && page_unprotect(address, pc, puc)) {
return 1;
}
return 0;
}
#elif defined (TARGET_PPC)
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
- int is_write, sigset_t *old_set)
+ int is_write, sigset_t *old_set,
+ void *puc)
{
TranslationBlock *tb;
+ int ret;
-#if 0
+#if 1
if (cpu_single_env)
env = cpu_single_env; /* XXX: find a correct solution for multithread */
#endif
pc, address, is_write, *(unsigned long *)old_set);
#endif
/* XXX: locking issue */
- if (is_write && page_unprotect(address)) {
+ if (is_write && page_unprotect(address, pc, puc)) {
return 1;
}
+ /* see if it is an MMU fault */
+ ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
+ if (ret < 0)
+ return 0; /* not an MMU fault */
+ if (ret == 0)
+ return 1; /* the MMU fault was handled without causing real CPU fault */
+
/* now we have a real cpu fault */
tb = tb_find_pc(pc);
if (tb) {
/* the PC is inside the translated code. It means that we have
a virtual CPU fault */
- cpu_restore_state(tb, env, pc);
+ cpu_restore_state(tb, env, pc, puc);
}
+ if (ret == 1) {
#if 0
- printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
- env->eip, env->cr[2], env->error_code);
+ printf("PF exception: NIP=0x%08x error=0x%x %p\n",
+ env->nip, env->error_code, tb);
#endif
/* we restore the process signal mask as the sigreturn should
do it (XXX: use sigsetjmp) */
- sigprocmask(SIG_SETMASK, old_set, NULL);
- raise_exception_err(EXCP_PROGRAM, env->error_code);
+ sigprocmask(SIG_SETMASK, old_set, NULL);
+ do_raise_exception_err(env->exception_index, env->error_code);
+ } else {
+ /* activate soft MMU for this block */
+ cpu_resume_from_signal(env, puc);
+ }
/* never comes here */
return 1;
}
#if defined(__i386__)
+#if defined(USE_CODE_COPY)
+static void cpu_send_trap(unsigned long pc, int trap,
+ struct ucontext *uc)
+{
+ TranslationBlock *tb;
+
+ if (cpu_single_env)
+ env = cpu_single_env; /* XXX: find a correct solution for multithread */
+ /* now we have a real cpu fault */
+ tb = tb_find_pc(pc);
+ if (tb) {
+ /* the PC is inside the translated code. It means that we have
+ a virtual CPU fault */
+ cpu_restore_state(tb, env, pc, uc);
+ }
+ sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
+ raise_exception_err(trap, env->error_code);
+}
+#endif
+
int cpu_signal_handler(int host_signum, struct siginfo *info,
void *puc)
{
struct ucontext *uc = puc;
unsigned long pc;
-
+ int trapno;
+
#ifndef REG_EIP
/* for glibc 2.1 */
#define REG_EIP EIP
#define REG_TRAPNO TRAPNO
#endif
pc = uc->uc_mcontext.gregs[REG_EIP];
+ trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
+#if defined(TARGET_I386) && defined(USE_CODE_COPY)
+ if (trapno == 0x00 || trapno == 0x05) {
+ /* send division by zero or bound exception */
+ cpu_send_trap(pc, trapno, uc);
+ return 1;
+ } else
+#endif
+ return handle_cpu_signal(pc, (unsigned long)info->si_addr,
+ trapno == 0xe ?
+ (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
+ &uc->uc_sigmask, puc);
+}
+
+#elif defined(__x86_64__)
+
+int cpu_signal_handler(int host_signum, struct siginfo *info,
+ void *puc)
+{
+ struct ucontext *uc = puc;
+ unsigned long pc;
+
+ pc = uc->uc_mcontext.gregs[REG_RIP];
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
- &uc->uc_sigmask);
+ &uc->uc_sigmask, puc);
}
-#elif defined(__powerpc)
+#elif defined(__powerpc__)
+
+/***********************************************************************
+ * signal context platform-specific definitions
+ * From Wine
+ */
+#ifdef linux
+/* All Registers access - only for local access */
+# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
+/* Gpr Registers access */
+# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
+# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
+# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
+# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
+# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
+# define LR_sig(context) REG_sig(link, context) /* Link register */
+# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
+/* Float Registers access */
+# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
+# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
+/* Exception Registers access */
+# define DAR_sig(context) REG_sig(dar, context)
+# define DSISR_sig(context) REG_sig(dsisr, context)
+# define TRAP_sig(context) REG_sig(trap, context)
+#endif /* linux */
+
+#ifdef __APPLE__
+# include <sys/ucontext.h>
+typedef struct ucontext SIGCONTEXT;
+/* All Registers access - only for local access */
+# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
+# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
+# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
+# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
+/* Gpr Registers access */
+# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
+# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
+# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
+# define CTR_sig(context) REG_sig(ctr, context)
+# define XER_sig(context) REG_sig(xer, context) /* Link register */
+# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
+# define CR_sig(context) REG_sig(cr, context) /* Condition register */
+/* Float Registers access */
+# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
+# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
+/* Exception Registers access */
+# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
+# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
+# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
+#endif /* __APPLE__ */
int cpu_signal_handler(int host_signum, struct siginfo *info,
void *puc)
{
struct ucontext *uc = puc;
- struct pt_regs *regs = uc->uc_mcontext.regs;
unsigned long pc;
int is_write;
- pc = regs->nip;
+ pc = IAR_sig(uc);
is_write = 0;
#if 0
/* ppc 4xx case */
- if (regs->dsisr & 0x00800000)
+ if (DSISR_sig(uc) & 0x00800000)
is_write = 1;
#else
- if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
+ if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
is_write = 1;
#endif
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
- is_write, &uc->uc_sigmask);
+ is_write, &uc->uc_sigmask, puc);
}
#elif defined(__alpha__)
}
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
- is_write, &uc->uc_sigmask);
+ is_write, &uc->uc_sigmask, puc);
}
#elif defined(__sparc__)
}
}
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
- is_write, sigmask);
+ is_write, sigmask, NULL);
}
#elif defined(__arm__)
is_write = 0;
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
is_write,
- &uc->uc_sigmask);
+ &uc->uc_sigmask, puc);
}
#else
#error host CPU specific signal handler needed
#endif
+
+#endif /* !defined(CONFIG_SOFTMMU) */
projects / qemu.git / blobdiff