#include "hw/xen.h"
#include "qemu-timer.h"
#include "memory.h"
+#include "dma.h"
#include "exec-memory.h"
#if defined(CONFIG_USER_ONLY)
#include <qemu.h>
AddressSpace address_space_io;
AddressSpace address_space_memory;
+DMAContext dma_context_memory;
MemoryRegion io_mem_ram, io_mem_rom, io_mem_unassigned, io_mem_notdirty;
static MemoryRegion io_mem_subpage_ram;
static void io_mem_init(void);
static void memory_map_init(void);
+static void *qemu_safe_ram_ptr(ram_addr_t addr);
static MemoryRegion io_mem_watch;
#endif
+static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
+ tb_page_addr_t phys_page2);
/* statistics */
static int tb_flush_count;
}
-static void phys_page_set_level(PhysPageEntry *lp, target_phys_addr_t *index,
- target_phys_addr_t *nb, uint16_t leaf,
+static void phys_page_set_level(PhysPageEntry *lp, hwaddr *index,
+ hwaddr *nb, uint16_t leaf,
int level)
{
PhysPageEntry *p;
int i;
- target_phys_addr_t step = (target_phys_addr_t)1 << (level * L2_BITS);
+ hwaddr step = (hwaddr)1 << (level * L2_BITS);
if (!lp->is_leaf && lp->ptr == PHYS_MAP_NODE_NIL) {
lp->ptr = phys_map_node_alloc();
}
static void phys_page_set(AddressSpaceDispatch *d,
- target_phys_addr_t index, target_phys_addr_t nb,
+ hwaddr index, hwaddr nb,
uint16_t leaf)
{
/* Wildly overreserve - it doesn't matter much. */
phys_page_set_level(&d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
}
-MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, target_phys_addr_t index)
+MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr index)
{
PhysPageEntry lp = d->phys_map;
PhysPageEntry *p;
void cpu_exec_init(CPUArchState *env)
{
+#ifndef CONFIG_USER_ONLY
+ CPUState *cpu = ENV_GET_CPU(env);
+#endif
CPUArchState **penv;
int cpu_index;
QTAILQ_INIT(&env->breakpoints);
QTAILQ_INIT(&env->watchpoints);
#ifndef CONFIG_USER_ONLY
- env->thread_id = qemu_get_thread_id();
+ cpu->thread_id = qemu_get_thread_id();
#endif
*penv = env;
#if defined(CONFIG_USER_ONLY)
/* add a new TB and link it to the physical page tables. phys_page2 is
(-1) to indicate that only one page contains the TB. */
-void tb_link_page(TranslationBlock *tb,
- tb_page_addr_t phys_pc, tb_page_addr_t phys_page2)
+static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
+ tb_page_addr_t phys_page2)
{
unsigned int h;
TranslationBlock **ptb;
mmap_unlock();
}
+#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU)
+/* check whether the given addr is in TCG generated code buffer or not */
+bool is_tcg_gen_code(uintptr_t tc_ptr)
+{
+ /* This can be called during code generation, code_gen_buffer_max_size
+ is used instead of code_gen_ptr for upper boundary checking */
+ return (tc_ptr >= (uintptr_t)code_gen_buffer &&
+ tc_ptr < (uintptr_t)(code_gen_buffer + code_gen_buffer_max_size));
+}
+#endif
+
/* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
tb[1].tc_ptr. Return NULL if not found */
TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
tb_invalidate_phys_page_range(pc, pc + 1, 0);
}
#else
-void tb_invalidate_phys_addr(target_phys_addr_t addr)
+void tb_invalidate_phys_addr(hwaddr addr)
{
ram_addr_t ram_addr;
MemoryRegionSection *section;
/* mask must never be zero, except for A20 change call */
static void tcg_handle_interrupt(CPUArchState *env, int mask)
{
+ CPUState *cpu = ENV_GET_CPU(env);
int old_mask;
old_mask = env->interrupt_request;
* If called from iothread context, wake the target cpu in
* case its halted.
*/
- if (!qemu_cpu_is_self(env)) {
- qemu_cpu_kick(env);
+ if (!qemu_cpu_is_self(cpu)) {
+ qemu_cpu_kick(cpu);
return;
}
}
}
-int cpu_physical_memory_set_dirty_tracking(int enable)
+static int cpu_physical_memory_set_dirty_tracking(int enable)
{
int ret = 0;
in_migration = enable;
return ret;
}
-target_phys_addr_t memory_region_section_get_iotlb(CPUArchState *env,
+hwaddr memory_region_section_get_iotlb(CPUArchState *env,
MemoryRegionSection *section,
target_ulong vaddr,
- target_phys_addr_t paddr,
+ hwaddr paddr,
int prot,
target_ulong *address)
{
- target_phys_addr_t iotlb;
+ hwaddr iotlb;
CPUWatchpoint *wp;
if (memory_region_is_ram(section->mr)) {
#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
typedef struct subpage_t {
MemoryRegion iomem;
- target_phys_addr_t base;
+ hwaddr base;
uint16_t sub_section[TARGET_PAGE_SIZE];
} subpage_t;
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
uint16_t section);
-static subpage_t *subpage_init(target_phys_addr_t base);
+static subpage_t *subpage_init(hwaddr base);
static void destroy_page_desc(uint16_t section_index)
{
MemoryRegionSection *section = &phys_sections[section_index];
static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)
{
subpage_t *subpage;
- target_phys_addr_t base = section->offset_within_address_space
+ hwaddr base = section->offset_within_address_space
& TARGET_PAGE_MASK;
MemoryRegionSection *existing = phys_page_find(d, base >> TARGET_PAGE_BITS);
MemoryRegionSection subsection = {
.offset_within_address_space = base,
.size = TARGET_PAGE_SIZE,
};
- target_phys_addr_t start, end;
+ hwaddr start, end;
assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
static void register_multipage(AddressSpaceDispatch *d, MemoryRegionSection *section)
{
- target_phys_addr_t start_addr = section->offset_within_address_space;
+ hwaddr start_addr = section->offset_within_address_space;
ram_addr_t size = section->size;
- target_phys_addr_t addr;
+ hwaddr addr;
uint16_t section_index = phys_section_add(section);
assert(size);
/* Return a host pointer to ram allocated with qemu_ram_alloc.
* Same as qemu_get_ram_ptr but avoid reordering ramblocks.
*/
-void *qemu_safe_ram_ptr(ram_addr_t addr)
+static void *qemu_safe_ram_ptr(ram_addr_t addr)
{
RAMBlock *block;
/* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr
* but takes a size argument */
-void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size)
+static void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size)
{
if (*size == 0) {
return NULL;
return ram_addr;
}
-static uint64_t unassigned_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
#ifdef DEBUG_UNASSIGNED
return 0;
}
-static void unassigned_mem_write(void *opaque, target_phys_addr_t addr,
+static void unassigned_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
#ifdef DEBUG_UNASSIGNED
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t error_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t error_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
abort();
}
-static void error_mem_write(void *opaque, target_phys_addr_t addr,
+static void error_mem_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
abort();
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void notdirty_mem_write(void *opaque, target_phys_addr_t ram_addr,
+static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
uint64_t val, unsigned size)
{
int dirty_flags;
/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
so these check for a hit then pass through to the normal out-of-line
phys routines. */
-static uint64_t watch_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t watch_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
}
}
-static void watch_mem_write(void *opaque, target_phys_addr_t addr,
+static void watch_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t subpage_read(void *opaque, target_phys_addr_t addr,
+static uint64_t subpage_read(void *opaque, hwaddr addr,
unsigned len)
{
subpage_t *mmio = opaque;
return io_mem_read(section->mr, addr, len);
}
-static void subpage_write(void *opaque, target_phys_addr_t addr,
+static void subpage_write(void *opaque, hwaddr addr,
uint64_t value, unsigned len)
{
subpage_t *mmio = opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t subpage_ram_read(void *opaque, target_phys_addr_t addr,
+static uint64_t subpage_ram_read(void *opaque, hwaddr addr,
unsigned size)
{
ram_addr_t raddr = addr;
}
}
-static void subpage_ram_write(void *opaque, target_phys_addr_t addr,
+static void subpage_ram_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
ram_addr_t raddr = addr;
return 0;
}
-static subpage_t *subpage_init(target_phys_addr_t base)
+static subpage_t *subpage_init(hwaddr base)
{
subpage_t *mmio;
return phys_section_add(§ion);
}
-MemoryRegion *iotlb_to_region(target_phys_addr_t index)
+MemoryRegion *iotlb_to_region(hwaddr index)
{
return phys_sections[index & ~TARGET_PAGE_MASK].mr;
}
memory_listener_register(&core_memory_listener, &address_space_memory);
memory_listener_register(&io_memory_listener, &address_space_io);
memory_listener_register(&tcg_memory_listener, &address_space_memory);
+
+ dma_context_init(&dma_context_memory, &address_space_memory,
+ NULL, NULL, NULL);
}
MemoryRegion *get_system_memory(void)
#else
-static void invalidate_and_set_dirty(target_phys_addr_t addr,
- target_phys_addr_t length)
+static void invalidate_and_set_dirty(hwaddr addr,
+ hwaddr length)
{
if (!cpu_physical_memory_is_dirty(addr)) {
/* invalidate code */
xen_modified_memory(addr, length);
}
-void address_space_rw(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf,
+void address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
int len, bool is_write)
{
AddressSpaceDispatch *d = as->dispatch;
int l;
uint8_t *ptr;
uint32_t val;
- target_phys_addr_t page;
+ hwaddr page;
MemoryRegionSection *section;
while (len > 0) {
if (is_write) {
if (!memory_region_is_ram(section->mr)) {
- target_phys_addr_t addr1;
+ hwaddr addr1;
addr1 = memory_region_section_addr(section, addr);
/* XXX: could force cpu_single_env to NULL to avoid
potential bugs */
} else {
if (!(memory_region_is_ram(section->mr) ||
memory_region_is_romd(section->mr))) {
- target_phys_addr_t addr1;
+ hwaddr addr1;
/* I/O case */
addr1 = memory_region_section_addr(section, addr);
if (l >= 4 && ((addr1 & 3) == 0)) {
}
}
-void address_space_write(AddressSpace *as, target_phys_addr_t addr,
+void address_space_write(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len)
{
address_space_rw(as, addr, (uint8_t *)buf, len, true);
* @addr: address within that address space
* @buf: buffer with the data transferred
*/
-void address_space_read(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf, int len)
+void address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len)
{
address_space_rw(as, addr, buf, len, false);
}
-void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
+void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
int len, int is_write)
{
return address_space_rw(&address_space_memory, addr, buf, len, is_write);
}
/* used for ROM loading : can write in RAM and ROM */
-void cpu_physical_memory_write_rom(target_phys_addr_t addr,
+void cpu_physical_memory_write_rom(hwaddr addr,
const uint8_t *buf, int len)
{
AddressSpaceDispatch *d = address_space_memory.dispatch;
int l;
uint8_t *ptr;
- target_phys_addr_t page;
+ hwaddr page;
MemoryRegionSection *section;
while (len > 0) {
typedef struct {
void *buffer;
- target_phys_addr_t addr;
- target_phys_addr_t len;
+ hwaddr addr;
+ hwaddr len;
} BounceBuffer;
static BounceBuffer bounce;
return client;
}
-void cpu_unregister_map_client(void *_client)
+static void cpu_unregister_map_client(void *_client)
{
MapClient *client = (MapClient *)_client;
* likely to succeed.
*/
void *address_space_map(AddressSpace *as,
- target_phys_addr_t addr,
- target_phys_addr_t *plen,
+ hwaddr addr,
+ hwaddr *plen,
bool is_write)
{
AddressSpaceDispatch *d = as->dispatch;
- target_phys_addr_t len = *plen;
- target_phys_addr_t todo = 0;
+ hwaddr len = *plen;
+ hwaddr todo = 0;
int l;
- target_phys_addr_t page;
+ hwaddr page;
MemoryRegionSection *section;
ram_addr_t raddr = RAM_ADDR_MAX;
ram_addr_t rlen;
* Will also mark the memory as dirty if is_write == 1. access_len gives
* the amount of memory that was actually read or written by the caller.
*/
-void address_space_unmap(AddressSpace *as, void *buffer, target_phys_addr_t len,
- int is_write, target_phys_addr_t access_len)
+void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
+ int is_write, hwaddr access_len)
{
if (buffer != bounce.buffer) {
if (is_write) {
cpu_notify_map_clients();
}
-void *cpu_physical_memory_map(target_phys_addr_t addr,
- target_phys_addr_t *plen,
+void *cpu_physical_memory_map(hwaddr addr,
+ hwaddr *plen,
int is_write)
{
return address_space_map(&address_space_memory, addr, plen, is_write);
}
-void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
- int is_write, target_phys_addr_t access_len)
+void cpu_physical_memory_unmap(void *buffer, hwaddr len,
+ int is_write, hwaddr access_len)
{
return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
}
/* warning: addr must be aligned */
-static inline uint32_t ldl_phys_internal(target_phys_addr_t addr,
+static inline uint32_t ldl_phys_internal(hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
return val;
}
-uint32_t ldl_phys(target_phys_addr_t addr)
+uint32_t ldl_phys(hwaddr addr)
{
return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t ldl_le_phys(target_phys_addr_t addr)
+uint32_t ldl_le_phys(hwaddr addr)
{
return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t ldl_be_phys(target_phys_addr_t addr)
+uint32_t ldl_be_phys(hwaddr addr)
{
return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned */
-static inline uint64_t ldq_phys_internal(target_phys_addr_t addr,
+static inline uint64_t ldq_phys_internal(hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
return val;
}
-uint64_t ldq_phys(target_phys_addr_t addr)
+uint64_t ldq_phys(hwaddr addr)
{
return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
}
-uint64_t ldq_le_phys(target_phys_addr_t addr)
+uint64_t ldq_le_phys(hwaddr addr)
{
return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
}
-uint64_t ldq_be_phys(target_phys_addr_t addr)
+uint64_t ldq_be_phys(hwaddr addr)
{
return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
-uint32_t ldub_phys(target_phys_addr_t addr)
+uint32_t ldub_phys(hwaddr addr)
{
uint8_t val;
cpu_physical_memory_read(addr, &val, 1);
}
/* warning: addr must be aligned */
-static inline uint32_t lduw_phys_internal(target_phys_addr_t addr,
+static inline uint32_t lduw_phys_internal(hwaddr addr,
enum device_endian endian)
{
uint8_t *ptr;
return val;
}
-uint32_t lduw_phys(target_phys_addr_t addr)
+uint32_t lduw_phys(hwaddr addr)
{
return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t lduw_le_phys(target_phys_addr_t addr)
+uint32_t lduw_le_phys(hwaddr addr)
{
return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t lduw_be_phys(target_phys_addr_t addr)
+uint32_t lduw_be_phys(hwaddr addr)
{
return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned. The ram page is not masked as dirty
and the code inside is not invalidated. It is useful if the dirty
bits are used to track modified PTEs */
-void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
+void stl_phys_notdirty(hwaddr addr, uint32_t val)
{
uint8_t *ptr;
MemoryRegionSection *section;
}
}
-void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
+void stq_phys_notdirty(hwaddr addr, uint64_t val)
{
uint8_t *ptr;
MemoryRegionSection *section;
}
/* warning: addr must be aligned */
-static inline void stl_phys_internal(target_phys_addr_t addr, uint32_t val,
+static inline void stl_phys_internal(hwaddr addr, uint32_t val,
enum device_endian endian)
{
uint8_t *ptr;
}
}
-void stl_phys(target_phys_addr_t addr, uint32_t val)
+void stl_phys(hwaddr addr, uint32_t val)
{
stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
}
-void stl_le_phys(target_phys_addr_t addr, uint32_t val)
+void stl_le_phys(hwaddr addr, uint32_t val)
{
stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
}
-void stl_be_phys(target_phys_addr_t addr, uint32_t val)
+void stl_be_phys(hwaddr addr, uint32_t val)
{
stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
-void stb_phys(target_phys_addr_t addr, uint32_t val)
+void stb_phys(hwaddr addr, uint32_t val)
{
uint8_t v = val;
cpu_physical_memory_write(addr, &v, 1);
}
/* warning: addr must be aligned */
-static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val,
+static inline void stw_phys_internal(hwaddr addr, uint32_t val,
enum device_endian endian)
{
uint8_t *ptr;
}
}
-void stw_phys(target_phys_addr_t addr, uint32_t val)
+void stw_phys(hwaddr addr, uint32_t val)
{
stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
}
-void stw_le_phys(target_phys_addr_t addr, uint32_t val)
+void stw_le_phys(hwaddr addr, uint32_t val)
{
stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
}
-void stw_be_phys(target_phys_addr_t addr, uint32_t val)
+void stw_be_phys(hwaddr addr, uint32_t val)
{
stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
-void stq_phys(target_phys_addr_t addr, uint64_t val)
+void stq_phys(hwaddr addr, uint64_t val)
{
val = tswap64(val);
cpu_physical_memory_write(addr, &val, 8);
}
-void stq_le_phys(target_phys_addr_t addr, uint64_t val)
+void stq_le_phys(hwaddr addr, uint64_t val)
{
val = cpu_to_le64(val);
cpu_physical_memory_write(addr, &val, 8);
}
-void stq_be_phys(target_phys_addr_t addr, uint64_t val)
+void stq_be_phys(hwaddr addr, uint64_t val)
{
val = cpu_to_be64(val);
cpu_physical_memory_write(addr, &val, 8);
uint8_t *buf, int len, int is_write)
{
int l;
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
target_ulong page;
while (len > 0) {
#endif
#ifndef CONFIG_USER_ONLY
-bool cpu_physical_memory_is_io(target_phys_addr_t phys_addr)
+bool cpu_physical_memory_is_io(hwaddr phys_addr)
{
MemoryRegionSection *section;
projects / qemu.git / blobdiff