#define APB_DPRINTF(fmt, ...)
#endif
-typedef a_target_phys_addr a_pci_addr;
+typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"
typedef struct APBState {
PCIHostState host_state;
} APBState;
-static void pci_apb_config_writel (void *opaque, a_target_phys_addr addr,
+static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
APBState *s = opaque;
}
static uint32_t pci_apb_config_readl (void *opaque,
- a_target_phys_addr addr)
+ target_phys_addr_t addr)
{
APBState *s = opaque;
uint32_t val;
&pci_apb_config_readl,
};
-static void apb_config_writel (void *opaque, a_target_phys_addr addr,
+static void apb_config_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
//PCIBus *s = opaque;
}
static uint32_t apb_config_readl (void *opaque,
- a_target_phys_addr addr)
+ target_phys_addr_t addr)
{
//PCIBus *s = opaque;
uint32_t val;
&pci_host_data_readl,
};
-static void pci_apb_iowriteb (void *opaque, a_target_phys_addr addr,
+static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outb(addr & IOPORTS_MASK, val);
}
-static void pci_apb_iowritew (void *opaque, a_target_phys_addr addr,
+static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outw(addr & IOPORTS_MASK, val);
}
-static void pci_apb_iowritel (void *opaque, a_target_phys_addr addr,
+static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outl(addr & IOPORTS_MASK, val);
}
-static uint32_t pci_apb_ioreadb (void *opaque, a_target_phys_addr addr)
+static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
return val;
}
-static uint32_t pci_apb_ioreadw (void *opaque, a_target_phys_addr addr)
+static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
return val;
}
-static uint32_t pci_apb_ioreadl (void *opaque, a_target_phys_addr addr)
+static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
qemu_set_irq(pic[irq_num], level);
}
-PCIBus *pci_apb_init(a_target_phys_addr special_base,
- a_target_phys_addr mem_base,
+PCIBus *pci_apb_init(target_phys_addr_t special_base,
+ target_phys_addr_t mem_base,
qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
{
DeviceState *dev;